;------------------------------------------------------------------------
;                                                                       |
;   FILE        :sfr64.inc                                              |
;   DATE        :Fri, Jan 17, 2014                                      |
;   DESCRIPTION :define the sfr register. (for Assembler language)      |
;   CPU GROUP   :64                                                     |
;                                                                       |
;   This file is generated by Renesas Project Generator (Ver.4.19).     |
;   NOTE:THIS IS A TYPICAL EXAMPLE.                                     |
;------------------------------------------------------------------------
;*******************************************************************************
;*
;* Device     : R5F3640xxFx(M16C/64 group)
;*
;* File Name  : sfr64.inc
;*
;* Abstract   : Definition of I/O Register.
;*
;* History    : 1.00  (2007-11-26)  [Hardware Manual Revision : 1.04]
;*            : 1.01  (2009-01-23)  [Hardware Manual Revision : 1.05]
;*
;* Copyright (C) 2007 (2009 - 2010) Renesas Electronics Corporation.
;* and Renesas Solutions Corporation. All rights reserved.
;*
;*******************************************************************************

;*******************************************************************************
;*  Definition of SFR                                                          *
;*******************************************************************************
;*-----------------------------------------------------------------------------*
;*  Processor Mode Register 0                                                  *
;*-----------------------------------------------------------------------------*
pm0			.equ	0004h
;
pm00			.btequ		0,pm0		; Processor mode bit
pm01			.btequ		1,pm0		; Processor mode bit
pm02			.btequ		2,pm0		; R/W mode select bit
pm03			.btequ		3,pm0		; Software reset bit
pm04			.btequ		4,pm0		; Multiplexed bus space select bit
pm05			.btequ		5,pm0		; Multiplexed bus space select bit
pm06			.btequ		6,pm0		; Port P4_0 to P4_3 function select bit
pm07			.btequ		7,pm0		; BCLK output disable bit
;
;*-----------------------------------------------------------------------------*
;*  Processor Mode Register 1                                                  *
;*-----------------------------------------------------------------------------*
pm1			.equ	0005h
;
pm10			.btequ		0,pm1		; CS2~ area switch bit(data flash enable bit)
pm11			.btequ		1,pm1		; Port P3_7 to P3_4 function select bit
pm12			.btequ		2,pm1		; Watchdog timer function select bit
pm13			.btequ		3,pm1		; Internal reserved area expansion bit
pm14			.btequ		4,pm1		; Memory area expansion bit
pm15			.btequ		5,pm1		; Memory area expansion bit
pm17			.btequ		7,pm1		; Wait bit
;
;*-----------------------------------------------------------------------------*
;*  System Clock Control Register 0                                            *
;*-----------------------------------------------------------------------------*
cm0			.equ	0006h
;
cm00			.btequ		0,cm0		; Clock output function select bit(valid only in single-chip mode)
cm01			.btequ		1,cm0		; Clock output function select bit(valid only in single-chip mode)
cm02			.btequ		2,cm0		; Wait mode peripheral function clock stop bit
cm03			.btequ		3,cm0		; XCIN-XCOUT drive capacity select bit
cm04			.btequ		4,cm0		; Port XC select bit
cm05			.btequ		5,cm0		; Main clock stop bit
cm06			.btequ		6,cm0		; Main clock division select bit 0
cm07			.btequ		7,cm0		; System clock select bit
;
;*-----------------------------------------------------------------------------*
;*  System Clock Control Register 1                                            *
;*-----------------------------------------------------------------------------*
cm1			.equ	0007h
;
cm10			.btequ		0,cm1		; All clock stop control bit
cm11			.btequ		1,cm1		; System clock select bit 1
cm14			.btequ		4,cm1		; 125kHz on-chip oscillator stop bit
cm15			.btequ		5,cm1		; XIN-XOUT drive capacity select bit
cm16			.btequ		6,cm1		; Main clock division select bit 1
cm17			.btequ		7,cm1		; Main clock division select bit 1
;
;*-----------------------------------------------------------------------------*
;*  Chip Select Control Register                                               *
;*-----------------------------------------------------------------------------*
csr			.equ	0008h
;
cs0				.btequ		0,csr		; CS0~ output enable bit
cs1				.btequ		1,csr		; CS1~ output enable bit
cs2				.btequ		2,csr		; CS2~ output enable bit
cs3				.btequ		3,csr		; CS3~ output enable bit
cs0w			.btequ		4,csr		; CS0~ wait bit
cs1w			.btequ		5,csr		; CS1~ wait bit
cs2w			.btequ		6,csr		; CS2~ wait bit
cs3w			.btequ		7,csr		; CS3~ wait bit
;
;*-----------------------------------------------------------------------------*
;*  Protect Register                                                           *
;*-----------------------------------------------------------------------------*
prcr		.equ	000Ah
;
prc0			.btequ		0,prcr		; Protect bit 0
prc1			.btequ		1,prcr		; Protect bit 1
prc2			.btequ		2,prcr		; Protect bit 2
prc3			.btequ		3,prcr		; Protect bit 3
prc6			.btequ		6,prcr		; Protect bit 6
;
;*-----------------------------------------------------------------------------*
;*  Data Bank Register                                                         *
;*-----------------------------------------------------------------------------*
dbr			.equ	000Bh
;
ofs				.btequ		2,dbr		; Offset bit
bsr0			.btequ		3,dbr		; Bank select bit
bsr1			.btequ		4,dbr		; Bank select bit
bsr2			.btequ		5,dbr		; Bank select bit
;
;*-----------------------------------------------------------------------------*
;*  Oscillation Stop Detection Register                                        *
;*-----------------------------------------------------------------------------*
cm2			.equ	000Ch
;
cm20			.btequ		0,cm2		; Oscillation stop and re-oscillation detection enable bit
cm21			.btequ		1,cm2		; System clock select bit 2
cm22			.btequ		2,cm2		; Oscillation stop and re-oscillation detection flag
cm23			.btequ		3,cm2		; XIN monitor flag
cm27			.btequ		7,cm2		; Operation select bit(when an oscillation stops and re-oscillation is detected)
;
;*-----------------------------------------------------------------------------*
;*  Program 2 Area Control Register                                            *
;*-----------------------------------------------------------------------------*
prg2c		.equ	0010h
;
prg2c0			.btequ		0,prg2c		; Program ROM 2 disable bit
;
;*-----------------------------------------------------------------------------*
;*  Peripheral Clock Select Register                                           *
;*-----------------------------------------------------------------------------*
pclkr		.equ	0012h
;
pclk0			.btequ		0,pclkr		; Timers A and B clock select bit(clock source for Timers A, B, and the dead time timer)
pclk1			.btequ		1,pclkr		; SI/O clock select bit(clock source for UART0 to UART2, UART5 to UART7,SI/O3, and SI/O4)
;
;*-----------------------------------------------------------------------------*
;*  Clock Prescaler Reset Flag                                                 *
;*-----------------------------------------------------------------------------*
cpsrf		.equ	0015h
;
cpsr			.btequ		7,cpsrf		; Clock prescaler reset flag
;
;*-----------------------------------------------------------------------------*
;*  Reset Source Determine Flag                                                *
;*-----------------------------------------------------------------------------*
rstfr		.equ	0018h
;
cwr				.btequ		0,rstfr		; Cold start-up/warm start determine flag
;
;*-----------------------------------------------------------------------------*
;*  Voltage Detection 2 Circuit Flag Register                                  *
;*-----------------------------------------------------------------------------*
vcr1		.equ	0019h
;
vc13			.btequ		3,vcr1		; Low-voltage monitor flag
;
;*-----------------------------------------------------------------------------*
;*  Voltage Detection Circuit Operation Enable Register                        *
;*-----------------------------------------------------------------------------*
vcr2		.equ	001Ah
;
vc25			.btequ		5,vcr2		; Voltage detection 0 enable bit
vc27			.btequ		7,vcr2		; Low voltage monitor bit
;
;*-----------------------------------------------------------------------------*
;*  Chip Select Expansion Control Register                                     *
;*-----------------------------------------------------------------------------*
cse			.equ	001Bh
;
cse00w			.btequ		0,cse		; CS0~ wait expansion bit
cse01w			.btequ		1,cse		; CS0~ wait expansion bit
cse10w			.btequ		2,cse		; CS1~ wait expansion bit
cse11w			.btequ		3,cse		; CS1~ wait expansion bit
cse20w			.btequ		4,cse		; CS2~ wait expansion bit
cse21w			.btequ		5,cse		; CS2~ wait expansion bit
cse30w			.btequ		6,cse		; CS3~ wait expansion bit
cse31w			.btequ		7,cse		; CS3~ wait expansion bit
;
;*-----------------------------------------------------------------------------*
;*  PLL Control Register 0                                                     *
;*-----------------------------------------------------------------------------*
plc0		.equ	001Ch
;
plc00			.btequ		0,plc0		; PLL multiplying factor select bit
plc01			.btequ		1,plc0		; PLL multiplying factor select bit
plc02			.btequ		2,plc0		; PLL multiplying factor select bit
plc04			.btequ		4,plc0		; Reference frequency counter set bit
plc05			.btequ		5,plc0		; Reference frequency counter set bit
plc07			.btequ		7,plc0		; Operation enable bit
;
;*-----------------------------------------------------------------------------*
;*  Processor Mode Register 2                                                  *
;*-----------------------------------------------------------------------------*
pm2			.equ	001Eh
;
pm20			.btequ		0,pm2		; Specifying wait when accessing SFR at PLL operation
pm21			.btequ		1,pm2		; System clock protection bit
pm24			.btequ		4,pm2		; P8_5/NMI~ function select bit
pm25			.btequ		5,pm2		; D4INT clock provide enable bit
;
;*-----------------------------------------------------------------------------*
;*  Low Voltage Detection Interrupt Register                                   *
;*-----------------------------------------------------------------------------*
d4int		.equ	001Fh
;
d40				.btequ		0,d4int		; Low voltage detection interrupt enable bit
d41				.btequ		1,d4int		; STOP mode deactivation control bit
d42				.btequ		2,d4int		; Voltage change detection flag
d43				.btequ		3,d4int		; WDT overflow detect flag
df0				.btequ		4,d4int		; Sampling clock select bit
df1				.btequ		5,d4int		; Sampling clock select bit
;
;*-----------------------------------------------------------------------------*
;*  Voltage Monitor 0 Circuit Control Register                                 *
;*-----------------------------------------------------------------------------*
vw0c		.equ	002Ah
;
vw0c0			.btequ		0,vw0c		; Brown-out reset enable bit
vw0c1			.btequ		1,vw0c		; Voltage monitor 0 digital filter disable mode select bit
vw0f0			.btequ		4,vw0c		; Sampling clock select bit
vw0f1			.btequ		5,vw0c		; Sampling clock select bit
;
;*-----------------------------------------------------------------------------*
;*  INT7 Interrupt Control Register                                            *
;*-----------------------------------------------------------------------------*
int7ic		.equ	0042h
;
ilvl0_int7ic	.btequ		0,int7ic	; Interrupt priority level select bit
ilvl1_int7ic	.btequ		1,int7ic	; Interrupt priority level select bit
ilvl2_int7ic	.btequ		2,int7ic	; Interrupt priority level select bit
ir_int7ic		.btequ		3,int7ic	; Interrupt request bit
pol_int7ic		.btequ		4,int7ic	; Polarity select bit
;
;*-----------------------------------------------------------------------------*
;*  INT6 Interrupt Control Register                                            *
;*-----------------------------------------------------------------------------*
int6ic		.equ	0043h
;
ilvl0_int6ic	.btequ		0,int6ic	; Interrupt priority level select bit
ilvl1_int6ic	.btequ		1,int6ic	; Interrupt priority level select bit
ilvl2_int6ic	.btequ		2,int6ic	; Interrupt priority level select bit
ir_int6ic		.btequ		3,int6ic	; Interrupt request bit
pol_int6ic		.btequ		4,int6ic	; Polarity select bit
;
;*-----------------------------------------------------------------------------*
;*  INT3 Interrupt Control Register                                            *
;*-----------------------------------------------------------------------------*
int3ic		.equ	0044h
;
ilvl0_int3ic	.btequ		0,int3ic	; Interrupt priority level select bit
ilvl1_int3ic	.btequ		1,int3ic	; Interrupt priority level select bit
ilvl2_int3ic	.btequ		2,int3ic	; Interrupt priority level select bit
ir_int3ic		.btequ		3,int3ic	; Interrupt request bit
pol_int3ic		.btequ		4,int3ic	; Polarity select bit
;
;*-----------------------------------------------------------------------------*
;*  Timer B5 Interrupt Control Register                                        *
;*-----------------------------------------------------------------------------*
tb5ic		.equ	0045h
;
ilvl0_tb5ic		.btequ		0,tb5ic		; Interrupt priority level select bit
ilvl1_tb5ic		.btequ		1,tb5ic		; Interrupt priority level select bit
ilvl2_tb5ic		.btequ		2,tb5ic		; Interrupt priority level select bit
ir_tb5ic		.btequ		3,tb5ic		; Interrupt request bit
;
;*-----------------------------------------------------------------------------*
;*  Timer B4 Interrupt Control Register                                        *
;*-----------------------------------------------------------------------------*
tb4ic		.equ	0046h
;
ilvl0_tb4ic		.btequ		0,tb4ic		; Interrupt priority level select bit
ilvl1_tb4ic		.btequ		1,tb4ic		; Interrupt priority level select bit
ilvl2_tb4ic		.btequ		2,tb4ic		; Interrupt priority level select bit
ir_tb4ic		.btequ		3,tb4ic		; Interrupt request bit
;
;*-----------------------------------------------------------------------------*
;*  UART1 BUS Collision Detection InterruptControl Register                    *
;*-----------------------------------------------------------------------------*
u1bcnic		.equ	0046h
;
ilvl0_u1bcnic	.btequ		0,u1bcnic	; Interrupt priority level select bit
ilvl1_u1bcnic	.btequ		1,u1bcnic	; Interrupt priority level select bit
ilvl2_u1bcnic	.btequ		2,u1bcnic	; Interrupt priority level select bit
ir_u1bcnic		.btequ		3,u1bcnic	; Interrupt request bit
;
;*-----------------------------------------------------------------------------*
;*  Timer B3 Interrupt Control Register                                        *
;*-----------------------------------------------------------------------------*
tb3ic		.equ	0047h
;
ilvl0_tb3ic		.btequ		0,tb3ic		; Interrupt priority level select bit
ilvl1_tb3ic		.btequ		1,tb3ic		; Interrupt priority level select bit
ilvl2_tb3ic		.btequ		2,tb3ic		; Interrupt priority level select bit
ir_tb3ic		.btequ		3,tb3ic		; Interrupt request bit
;
;*-----------------------------------------------------------------------------*
;*  UART0 BUS Collision Detection InterruptControl Register                    *
;*-----------------------------------------------------------------------------*
u0bcnic		.equ	0047h
;
ilvl0_u0bcnic	.btequ		0,u0bcnic	; Interrupt priority level select bit
ilvl1_u0bcnic	.btequ		1,u0bcnic	; Interrupt priority level select bit
ilvl2_u0bcnic	.btequ		2,u0bcnic	; Interrupt priority level select bit
ir_u0bcnic		.btequ		3,u0bcnic	; Interrupt request bit
;
;*-----------------------------------------------------------------------------*
;*  SI/O4 Interrupt Control Register                                           *
;*-----------------------------------------------------------------------------*
s4ic		.equ	0048h
;
ilvl0_s4ic		.btequ		0,s4ic		; Interrupt priority level select bit
ilvl1_s4ic		.btequ		1,s4ic		; Interrupt priority level select bit
ilvl2_s4ic		.btequ		2,s4ic		; Interrupt priority level select bit
ir_s4ic			.btequ		3,s4ic		; Interrupt request bit
pol_s4ic		.btequ		4,s4ic		; Polarity select bit
;
;*-----------------------------------------------------------------------------*
;*  INT5 Interrupt Control Register                                            *
;*-----------------------------------------------------------------------------*
int5ic		.equ	0048h
;
ilvl0_int5ic	.btequ		0,int5ic	; Interrupt priority level select bit
ilvl1_int5ic	.btequ		1,int5ic	; Interrupt priority level select bit
ilvl2_int5ic	.btequ		2,int5ic	; Interrupt priority level select bit
ir_int5ic		.btequ		3,int5ic	; Interrupt request bit
pol_int5ic		.btequ		4,int5ic	; Polarity select bit
;
;*-----------------------------------------------------------------------------*
;*  SI/O3 Interrupt Control Register                                           *
;*-----------------------------------------------------------------------------*
s3ic		.equ	0049h
;
ilvl0_s3ic		.btequ		0,s3ic		; Interrupt priority level select bit
ilvl1_s3ic		.btequ		1,s3ic		; Interrupt priority level select bit
ilvl2_s3ic		.btequ		2,s3ic		; Interrupt priority level select bit
ir_s3ic			.btequ		3,s3ic		; Interrupt request bit
pol_s3ic		.btequ		4,s3ic		; Polarity select bit
;
;*-----------------------------------------------------------------------------*
;*  INT4 Interrupt Control Register                                            *
;*-----------------------------------------------------------------------------*
int4ic		.equ	0049h
;
ilvl0_int4ic	.btequ		0,int4ic	; Interrupt priority level select bit
ilvl1_int4ic	.btequ		1,int4ic	; Interrupt priority level select bit
ilvl2_int4ic	.btequ		2,int4ic	; Interrupt priority level select bit
ir_int4ic		.btequ		3,int4ic	; Interrupt request bit
pol_int4ic		.btequ		4,int4ic	; Polarity select bit
;
;*-----------------------------------------------------------------------------*
;*  UART2 BUS Collision Detection Interrupt Control Register                   *
;*-----------------------------------------------------------------------------*
bcnic		.equ	004Ah
;
ilvl0_bcnic		.btequ		0,bcnic		; Interrupt priority level select bit
ilvl1_bcnic		.btequ		1,bcnic		; Interrupt priority level select bit
ilvl2_bcnic		.btequ		2,bcnic		; Interrupt priority level select bit
ir_bcnic		.btequ		3,bcnic		; Interrupt request bit
;
;*-----------------------------------------------------------------------------*
;*  DMA0 Interrupt Control Register                                            *
;*-----------------------------------------------------------------------------*
dm0ic		.equ	004Bh
;
ilvl0_dm0ic		.btequ		0,dm0ic		; Interrupt priority level select bit
ilvl1_dm0ic		.btequ		1,dm0ic		; Interrupt priority level select bit
ilvl2_dm0ic		.btequ		2,dm0ic		; Interrupt priority level select bit
ir_dm0ic		.btequ		3,dm0ic		; Interrupt request bit
;
;*-----------------------------------------------------------------------------*
;*  DMA1 Interrupt Control Register                                            *
;*-----------------------------------------------------------------------------*
dm1ic		.equ	004Ch
;
ilvl0_dm1ic		.btequ		0,dm1ic		; Interrupt priority level select bit
ilvl1_dm1ic		.btequ		1,dm1ic		; Interrupt priority level select bit
ilvl2_dm1ic		.btequ		2,dm1ic		; Interrupt priority level select bit
ir_dm1ic		.btequ		3,dm1ic		; Interrupt request bit
;
;*-----------------------------------------------------------------------------*
;*  Key Input Interrupt Control Register                                       *
;*-----------------------------------------------------------------------------*
kupic		.equ	004Dh
;
ilvl0_kupic		.btequ		0,kupic		; Interrupt priority level select bit
ilvl1_kupic		.btequ		1,kupic		; Interrupt priority level select bit
ilvl2_kupic		.btequ		2,kupic		; Interrupt priority level select bit
ir_kupic		.btequ		3,kupic		; Interrupt request bit
;
;*-----------------------------------------------------------------------------*
;*  A/D Conversion Interrupt Control Register                                  *
;*-----------------------------------------------------------------------------*
adic		.equ	004Eh
;
ilvl0_adic		.btequ		0,adic		; Interrupt priority level select bit
ilvl1_adic		.btequ		1,adic		; Interrupt priority level select bit
ilvl2_adic		.btequ		2,adic		; Interrupt priority level select bit
ir_adic			.btequ		3,adic		; Interrupt request bit
;
;*-----------------------------------------------------------------------------*
;*  UART2 Transmit Interrupt Control Register                                  *
;*-----------------------------------------------------------------------------*
s2tic		.equ	004Fh
;
ilvl0_s2tic		.btequ		0,s2tic		; Interrupt priority level select bit
ilvl1_s2tic		.btequ		1,s2tic		; Interrupt priority level select bit
ilvl2_s2tic		.btequ		2,s2tic		; Interrupt priority level select bit
ir_s2tic		.btequ		3,s2tic		; Interrupt request bit
;
;*-----------------------------------------------------------------------------*
;*  UART2 Receive Interrupt Control Register                                   *
;*-----------------------------------------------------------------------------*
s2ric		.equ	0050h
;
ilvl0_s2ric		.btequ		0,s2ric		; Interrupt priority level select bit
ilvl1_s2ric		.btequ		1,s2ric		; Interrupt priority level select bit
ilvl2_s2ric		.btequ		2,s2ric		; Interrupt priority level select bit
ir_s2ric		.btequ		3,s2ric		; Interrupt request bit
;
;*-----------------------------------------------------------------------------*
;*  UART0 Transmit Interrupt Control Register                                  *
;*-----------------------------------------------------------------------------*
s0tic		.equ	0051h
;
ilvl0_s0tic		.btequ		0,s0tic		; Interrupt priority level select bit
ilvl1_s0tic		.btequ		1,s0tic		; Interrupt priority level select bit
ilvl2_s0tic		.btequ		2,s0tic		; Interrupt priority level select bit
ir_s0tic		.btequ		3,s0tic		; Interrupt request bit
;
;*-----------------------------------------------------------------------------*
;*  UART0 Receive Interrupt Control Register                                   *
;*-----------------------------------------------------------------------------*
s0ric		.equ	0052h
;
ilvl0_s0ric		.btequ		0,s0ric		; Interrupt priority level select bit
ilvl1_s0ric		.btequ		1,s0ric		; Interrupt priority level select bit
ilvl2_s0ric		.btequ		2,s0ric		; Interrupt priority level select bit
ir_s0ric		.btequ		3,s0ric		; Interrupt request bit
;
;*-----------------------------------------------------------------------------*
;*  UART1 Transmit Interrupt Control Register                                  *
;*-----------------------------------------------------------------------------*
s1tic		.equ	0053h
;
ilvl0_s1tic		.btequ		0,s1tic		; Interrupt priority level select bit
ilvl1_s1tic		.btequ		1,s1tic		; Interrupt priority level select bit
ilvl2_s1tic		.btequ		2,s1tic		; Interrupt priority level select bit
ir_s1tic		.btequ		3,s1tic		; Interrupt request bit
;
;*-----------------------------------------------------------------------------*
;*  UART1 Receive Interrupt Control Register                                   *
;*-----------------------------------------------------------------------------*
s1ric		.equ	0054h
;
ilvl0_s1ric		.btequ		0,s1ric		; Interrupt priority level select bit
ilvl1_s1ric		.btequ		1,s1ric		; Interrupt priority level select bit
ilvl2_s1ric		.btequ		2,s1ric		; Interrupt priority level select bit
ir_s1ric		.btequ		3,s1ric		; Interrupt request bit
;
;*-----------------------------------------------------------------------------*
;*  Timer A0 Interrupt Control Register                                        *
;*-----------------------------------------------------------------------------*
ta0ic		.equ	0055h
;
ilvl0_ta0ic		.btequ		0,ta0ic		; Interrupt priority level select bit
ilvl1_ta0ic		.btequ		1,ta0ic		; Interrupt priority level select bit
ilvl2_ta0ic		.btequ		2,ta0ic		; Interrupt priority level select bit
ir_ta0ic		.btequ		3,ta0ic		; Interrupt request bit
;
;*-----------------------------------------------------------------------------*
;*  Timer A1 Interrupt Control Register                                        *
;*-----------------------------------------------------------------------------*
ta1ic		.equ	0056h
;
ilvl0_ta1ic		.btequ		0,ta1ic		; Interrupt priority level select bit
ilvl1_ta1ic		.btequ		1,ta1ic		; Interrupt priority level select bit
ilvl2_ta1ic		.btequ		2,ta1ic		; Interrupt priority level select bit
ir_ta1ic		.btequ		3,ta1ic		; Interrupt request bit
;
;*-----------------------------------------------------------------------------*
;*  Timer A2 Interrupt Control Register                                        *
;*-----------------------------------------------------------------------------*
ta2ic		.equ	0057h
;
ilvl0_ta2ic		.btequ		0,ta2ic		; Interrupt priority level select bit
ilvl1_ta2ic		.btequ		1,ta2ic		; Interrupt priority level select bit
ilvl2_ta2ic		.btequ		2,ta2ic		; Interrupt priority level select bit
ir_ta2ic		.btequ		3,ta2ic		; Interrupt request bit
;
;*-----------------------------------------------------------------------------*
;*  Timer A3 Interrupt Control Register                                        *
;*-----------------------------------------------------------------------------*
ta3ic		.equ	0058h
;
ilvl0_ta3ic		.btequ		0,ta3ic		; Interrupt priority level select bit
ilvl1_ta3ic		.btequ		1,ta3ic		; Interrupt priority level select bit
ilvl2_ta3ic		.btequ		2,ta3ic		; Interrupt priority level select bit
ir_ta3ic		.btequ		3,ta3ic		; Interrupt request bit
;
;*-----------------------------------------------------------------------------*
;*  Timer A4 Interrupt Control Register                                        *
;*-----------------------------------------------------------------------------*
ta4ic		.equ	0059h
;
ilvl0_ta4ic		.btequ		0,ta4ic		; Interrupt priority level select bit
ilvl1_ta4ic		.btequ		1,ta4ic		; Interrupt priority level select bit
ilvl2_ta4ic		.btequ		2,ta4ic		; Interrupt priority level select bit
ir_ta4ic		.btequ		3,ta4ic		; Interrupt request bit
;
;*-----------------------------------------------------------------------------*
;*  Timer B0 Interrupt Control Register                                        *
;*-----------------------------------------------------------------------------*
tb0ic		.equ	005Ah
;
ilvl0_tb0ic		.btequ		0,tb0ic		; Interrupt priority level select bit
ilvl1_tb0ic		.btequ		1,tb0ic		; Interrupt priority level select bit
ilvl2_tb0ic		.btequ		2,tb0ic		; Interrupt priority level select bit
ir_tb0ic		.btequ		3,tb0ic		; Interrupt request bit
;
;*-----------------------------------------------------------------------------*
;*  Timer B1 Interrupt Control Register                                        *
;*-----------------------------------------------------------------------------*
tb1ic		.equ	005Bh
;
ilvl0_tb1ic		.btequ		0,tb1ic		; Interrupt priority level select bit
ilvl1_tb1ic		.btequ		1,tb1ic		; Interrupt priority level select bit
ilvl2_tb1ic		.btequ		2,tb1ic		; Interrupt priority level select bit
ir_tb1ic		.btequ		3,tb1ic		; Interrupt request bit
;
;*-----------------------------------------------------------------------------*
;*  Timer B2 Interrupt Control Register                                        *
;*-----------------------------------------------------------------------------*
tb2ic		.equ	005Ch
;
ilvl0_tb2ic		.btequ		0,tb2ic		; Interrupt priority level select bit
ilvl1_tb2ic		.btequ		1,tb2ic		; Interrupt priority level select bit
ilvl2_tb2ic		.btequ		2,tb2ic		; Interrupt priority level select bit
ir_tb2ic		.btequ		3,tb2ic		; Interrupt request bit
;
;*-----------------------------------------------------------------------------*
;*  INT0 Interrupt Control Register                                            *
;*-----------------------------------------------------------------------------*
int0ic		.equ	005Dh
;
ilvl0_int0ic	.btequ		0,int0ic	; Interrupt priority level select bit
ilvl1_int0ic	.btequ		1,int0ic	; Interrupt priority level select bit
ilvl2_int0ic	.btequ		2,int0ic	; Interrupt priority level select bit
ir_int0ic		.btequ		3,int0ic	; Interrupt request bit
pol_int0ic		.btequ		4,int0ic	; Polarity select bit
;
;*-----------------------------------------------------------------------------*
;*  INT1 Interrupt Control Register                                            *
;*-----------------------------------------------------------------------------*
int1ic		.equ	005Eh
;
ilvl0_int1ic	.btequ		0,int1ic	; Interrupt priority level select bit
ilvl1_int1ic	.btequ		1,int1ic	; Interrupt priority level select bit
ilvl2_int1ic	.btequ		2,int1ic	; Interrupt priority level select bit
ir_int1ic		.btequ		3,int1ic	; Interrupt request bit
pol_int1ic		.btequ		4,int1ic	; Polarity select bit
;
;*-----------------------------------------------------------------------------*
;*  INT2 Interrupt Control Register                                            *
;*-----------------------------------------------------------------------------*
int2ic		.equ	005Fh
;
ilvl0_int2ic	.btequ		0,int2ic	; Interrupt priority level select bit
ilvl1_int2ic	.btequ		1,int2ic	; Interrupt priority level select bit
ilvl2_int2ic	.btequ		2,int2ic	; Interrupt priority level select bit
ir_int2ic		.btequ		3,int2ic	; Interrupt request bit
pol_int2ic		.btequ		4,int2ic	; Polarity select bit
;
;*-----------------------------------------------------------------------------*
;*  DMA2 Interrupt Control Register                                            *
;*-----------------------------------------------------------------------------*
dm2ic		.equ	0069h
;
ilvl0_dm2ic		.btequ		0,dm2ic		; Interrupt priority level select bit
ilvl1_dm2ic		.btequ		1,dm2ic		; Interrupt priority level select bit
ilvl2_dm2ic		.btequ		2,dm2ic		; Interrupt priority level select bit
ir_dm2ic		.btequ		3,dm2ic		; Interrupt request bit
;
;*-----------------------------------------------------------------------------*
;*  DMA3 Interrupt Control Register                                            *
;*-----------------------------------------------------------------------------*
dm3ic		.equ	006Ah
;
ilvl0_dm3ic		.btequ		0,dm3ic		; Interrupt priority level select bit
ilvl1_dm3ic		.btequ		1,dm3ic		; Interrupt priority level select bit
ilvl2_dm3ic		.btequ		2,dm3ic		; Interrupt priority level select bit
ir_dm3ic		.btequ		3,dm3ic		; Interrupt request bit
;
;*-----------------------------------------------------------------------------*
;*  UART5 BUS Collision Detection Interrupt Control Register                   *
;*-----------------------------------------------------------------------------*
u5bcnic		.equ	006Bh
;
ilvl0_u5bcnic	.btequ		0,u5bcnic	; Interrupt priority level select bit
ilvl1_u5bcnic	.btequ		1,u5bcnic	; Interrupt priority level select bit
ilvl2_u5bcnic	.btequ		2,u5bcnic	; Interrupt priority level select bit
ir_u5bcnic		.btequ		3,u5bcnic	; Interrupt request bit
;
;*-----------------------------------------------------------------------------*
;*  UART5 Transmit Interrupt Control Register                                  *
;*-----------------------------------------------------------------------------*
s5tic		.equ	006Ch
;
ilvl0_s5tic		.btequ		0,s5tic		; Interrupt priority level select bit
ilvl1_s5tic		.btequ		1,s5tic		; Interrupt priority level select bit
ilvl2_s5tic		.btequ		2,s5tic		; Interrupt priority level select bit
ir_s5tic		.btequ		3,s5tic		; Interrupt request bit
;
;*-----------------------------------------------------------------------------*
;*  UART5 Receive Interrupt Control Register                                   *
;*-----------------------------------------------------------------------------*
s5ric		.equ	006Dh
;
ilvl0_s5ric		.btequ		0,s5ric		; Interrupt priority level select bit
ilvl1_s5ric		.btequ		1,s5ric		; Interrupt priority level select bit
ilvl2_s5ric		.btequ		2,s5ric		; Interrupt priority level select bit
ir_s5ric		.btequ		3,s5ric		; Interrupt request bit
;
;*-----------------------------------------------------------------------------*
;*  UART6 BUS Collision Detection Interrupt Control Register                   *
;*-----------------------------------------------------------------------------*
u6bcnic		.equ	006Eh
;
ilvl0_u6bcnic	.btequ		0,u6bcnic	; Interrupt priority level select bit
ilvl1_u6bcnic	.btequ		1,u6bcnic	; Interrupt priority level select bit
ilvl2_u6bcnic	.btequ		2,u6bcnic	; Interrupt priority level select bit
ir_u6bcnic		.btequ		3,u6bcnic	; Interrupt request bit
;
;*-----------------------------------------------------------------------------*
;*  UART6 Transmit Interrupt Control Register                                  *
;*-----------------------------------------------------------------------------*
s6tic		.equ	006Fh
;
ilvl0_s6tic		.btequ		0,s6tic		; Interrupt priority level select bit
ilvl1_s6tic		.btequ		1,s6tic		; Interrupt priority level select bit
ilvl2_s6tic		.btequ		2,s6tic		; Interrupt priority level select bit
ir_s6tic		.btequ		3,s6tic		; Interrupt request bit
;
;*-----------------------------------------------------------------------------*
;*  UART6 Receive Interrupt Control Register                                   *
;*-----------------------------------------------------------------------------*
s6ric		.equ	0070h
;
ilvl0_s6ric		.btequ		0,s6ric		; Interrupt priority level select bit
ilvl1_s6ric		.btequ		1,s6ric		; Interrupt priority level select bit
ilvl2_s6ric		.btequ		2,s6ric		; Interrupt priority level select bit
ir_s6ric		.btequ		3,s6ric		; Interrupt request bit
;
;*-----------------------------------------------------------------------------*
;*  UART7 BUS Collision Detection Interrupt Control Register                   *
;*-----------------------------------------------------------------------------*
u7bcnic		.equ	0071h
;
ilvl0_u7bcnic	.btequ		0,u7bcnic	; Interrupt priority level select bit
ilvl1_u7bcnic	.btequ		1,u7bcnic	; Interrupt priority level select bit
ilvl2_u7bcnic	.btequ		2,u7bcnic	; Interrupt priority level select bit
ir_u7bcnic		.btequ		3,u7bcnic	; Interrupt request bit
;
;*-----------------------------------------------------------------------------*
;*  UART7 Transmit Interrupt Control Register                                  *
;*-----------------------------------------------------------------------------*
s7tic		.equ	0072h
;
ilvl0_s7tic		.btequ		0,s7tic		; Interrupt priority level select bit
ilvl1_s7tic		.btequ		1,s7tic		; Interrupt priority level select bit
ilvl2_s7tic		.btequ		2,s7tic		; Interrupt priority level select bit
ir_s7tic		.btequ		3,s7tic		; Interrupt request bit
;
;*-----------------------------------------------------------------------------*
;*  UART7 Receive Interrupt Control Register                                   *
;*-----------------------------------------------------------------------------*
s7ric		.equ	0073h
;
ilvl0_s7ric		.btequ		0,s7ric		; Interrupt priority level select bit
ilvl1_s7ric		.btequ		1,s7ric		; Interrupt priority level select bit
ilvl2_s7ric		.btequ		2,s7ric		; Interrupt priority level select bit
ir_s7ric		.btequ		3,s7ric		; Interrupt request bit
;
;*-----------------------------------------------------------------------------*
;*  DMA0 Source Pointer                                                        *
;*-----------------------------------------------------------------------------*
sar0		.equ	0180h
;
sar0l		.equ	sar0				; DMA0 Source Pointer(low 8bit)
sar0m		.equ	sar0+1				; DMA0 Source Pointer(mid 8bit)
sar0h		.equ	sar0+2				; DMA0 Source Pointer(high 8bit)
;
;*-----------------------------------------------------------------------------*
;*  DMA0 Destination Pointer                                                   *
;*-----------------------------------------------------------------------------*
dar0		.equ	0184h
;
dar0l		.equ	dar0				; DMA0 Destination Pointer(low 8bit)
dar0m		.equ	dar0+1				; DMA0 Destination Pointer(mid 8bit)
dar0h		.equ	dar0+2				; DMA0 Destination Pointer(high 8bit)
;
;*-----------------------------------------------------------------------------*
;*  DMA0 Transfer Counter                                                      *
;*-----------------------------------------------------------------------------*
tcr0		.equ	0188h
;
tcr0l		.equ	tcr0				; DMA0 Transfer Counter(low 8bit)
tcr0h		.equ	tcr0+1				; DMA0 Transfer Counter(high 8bit)
;
;*-----------------------------------------------------------------------------*
;*  DMA0 Control Register                                                      *
;*-----------------------------------------------------------------------------*
dm0con		.equ	018Ch
;
dmbit_dm0con	.btequ		0,dm0con	; Transfer unit bit select bit
dmasl_dm0con	.btequ		1,dm0con	; Repeat transfer mode select bit
dmas_dm0con		.btequ		2,dm0con	; DMA request bit
dmae_dm0con		.btequ		3,dm0con	; DMA enable bit
dsd_dm0con		.btequ		4,dm0con	; Source address direction select bit
dad_dm0con		.btequ		5,dm0con	; Destination address direction select bit
;
;*-----------------------------------------------------------------------------*
;*  DMA1 Source Pointer                                                        *
;*-----------------------------------------------------------------------------*
sar1		.equ	0190h
;
sar1l		.equ	sar1				; DMA1 Source Pointer(low 8bit)
sar1m		.equ	sar1+1				; DMA1 Source Pointer(mid 8bit)
sar1h		.equ	sar1+2				; DMA1 Source Pointer(high 8bit)
;
;*-----------------------------------------------------------------------------*
;*  DMA1 Destination Pointer                                                   *
;*-----------------------------------------------------------------------------*
dar1		.equ	0194h
;
dar1l		.equ	dar1				; DMA1 Destination Pointer(low 8bit)
dar1m		.equ	dar1+1				; DMA1 Destination Pointer(mid 8bit)
dar1h		.equ	dar1+2				; DMA1 Destination Pointer(high 8bit)
;
;*-----------------------------------------------------------------------------*
;*  DMA1 Transfer Counter                                                      *
;*-----------------------------------------------------------------------------*
tcr1		.equ	0198h
;
tcr1l		.equ	tcr1				; DMA1 Transfer Counter(low 8bit)
tcr1h		.equ	tcr1+1				; DMA1 Transfer Counter(high 8bit)
;
;*-----------------------------------------------------------------------------*
;*  DMA1 Control Register                                                      *
;*-----------------------------------------------------------------------------*
dm1con		.equ	019Ch
;
dmbit_dm1con	.btequ		0,dm1con	; Transfer unit bit select bit
dmasl_dm1con	.btequ		1,dm1con	; Repeat transfer mode select bit
dmas_dm1con		.btequ		2,dm1con	; DMA request bit
dmae_dm1con		.btequ		3,dm1con	; DMA enable bit
dsd_dm1con		.btequ		4,dm1con	; Source address direction select bit
dad_dm1con		.btequ		5,dm1con	; Destination address direction select bit
;
;*-----------------------------------------------------------------------------*
;*  DMA2 Source Pointer                                                        *
;*-----------------------------------------------------------------------------*
sar2		.equ	01A0h
;
sar2l		.equ	sar2				; DMA2 Source Pointer(low 8bit)
sar2m		.equ	sar2+1				; DMA2 Source Pointer(mid 8bit)
sar2h		.equ	sar2+2				; DMA2 Source Pointer(high 8bit)
;
;*-----------------------------------------------------------------------------*
;*  DMA2 Destination Pointer                                                   *
;*-----------------------------------------------------------------------------*
dar2		.equ	01A4h
;
dar2l		.equ	dar2				; DMA2 Destination Pointer(low 8bit)
dar2m		.equ	dar2+1				; DMA2 Destination Pointer(mid 8bit)
dar2h		.equ	dar2+2				; DMA2 Destination Pointer(high 8bit)
;
;*-----------------------------------------------------------------------------*
;*  DMA2 Transfer Counter                                                      *
;*-----------------------------------------------------------------------------*
tcr2		.equ	01A8h
;
tcr2l		.equ	tcr2				; DMA2 Transfer Counter(low 8bit)
tcr2h		.equ	tcr2+1				; DMA2 Transfer Counter(high 8bit)
;
;*-----------------------------------------------------------------------------*
;*  DMA2 Control Register                                                      *
;*-----------------------------------------------------------------------------*
dm2con		.equ	01ACh
;
dmbit_dm2con	.btequ		0,dm2con	; Transfer unit bit select bit
dmasl_dm2con	.btequ		1,dm2con	; Repeat transfer mode select bit
dmas_dm2con		.btequ		2,dm2con	; DMA request bit
dmae_dm2con		.btequ		3,dm2con	; DMA enable bit
dsd_dm2con		.btequ		4,dm2con	; Source address direction select bit
dad_dm2con		.btequ		5,dm2con	; Destination address direction select bit
;
;*-----------------------------------------------------------------------------*
;*  DMA3 Source Pointer                                                        *
;*-----------------------------------------------------------------------------*
sar3		.equ	01B0h
;
sar3l		.equ	sar3				; DMA3 Source Pointer(low 8bit)
sar3m		.equ	sar3+1				; DMA3 Source Pointer(mid 8bit)
sar3h		.equ	sar3+2				; DMA3 Source Pointer(high 8bit)
;
;*-----------------------------------------------------------------------------*
;*  DMA3 Destination Pointer                                                   *
;*-----------------------------------------------------------------------------*
dar3		.equ	01B4h
;
dar3l		.equ	dar3				; DMA3 Destination Pointer(low 8bit)
dar3m		.equ	dar3+1				; DMA3 Destination Pointer(mid 8bit)
dar3h		.equ	dar3+2				; DMA3 Destination Pointer(high 8bit)
;
;*-----------------------------------------------------------------------------*
;*  DMA3 Transfer Counter                                                      *
;*-----------------------------------------------------------------------------*
tcr3		.equ	01B8h
;
tcr3l		.equ	tcr3				; DMA3 Transfer Counter(low 8bit)
tcr3h		.equ	tcr3+1				; DMA3 Transfer Counter(high 8bit)
;
;*-----------------------------------------------------------------------------*
;*  DMA3 Control Register                                                      *
;*-----------------------------------------------------------------------------*
dm3con		.equ	01BCh
;
dmbit_dm3con	.btequ		0,dm3con	; Transfer unit bit select bit
dmasl_dm3con	.btequ		1,dm3con	; Repeat transfer mode select bit
dmas_dm3con		.btequ		2,dm3con	; DMA request bit
dmae_dm3con		.btequ		3,dm3con	; DMA enable bit
dsd_dm3con		.btequ		4,dm3con	; Source address direction select bit
dad_dm3con		.btequ		5,dm3con	; Destination address direction select bit
;
;*-----------------------------------------------------------------------------*
;*  Timer B Count Source Select Register 0                                     *
;*-----------------------------------------------------------------------------*
tbcs0		.equ	01C8h
;
tcs0_tbcs0		.btequ		0,tbcs0		; TB0 count source select bit
tcs1_tbcs0		.btequ		1,tbcs0		; TB0 count source select bit
tcs2_tbcs0		.btequ		2,tbcs0		; TB0 count source select bit
tcs3_tbcs0		.btequ		3,tbcs0		; TB0 count source option specified bit
tcs4_tbcs0		.btequ		4,tbcs0		; TB1 count source select bit
tcs5_tbcs0		.btequ		5,tbcs0		; TB1 count source select bit
tcs6_tbcs0		.btequ		6,tbcs0		; TB1 count source select bit
tcs7_tbcs0		.btequ		7,tbcs0		; TB1 count source option specified bit
;
;*-----------------------------------------------------------------------------*
;*  Timer B Count Source Select Register 1                                     *
;*-----------------------------------------------------------------------------*
tbcs1		.equ	01C9h
;
tcs0_tbcs1		.btequ		0,tbcs1		; TB2 count source select bit
tcs1_tbcs1		.btequ		1,tbcs1		; TB2 count source select bit
tcs2_tbcs1		.btequ		2,tbcs1		; TB2 count source select bit
tcs3_tbcs1		.btequ		3,tbcs1		; TB2 count source option specified bit
;
;*-----------------------------------------------------------------------------*
;*  Timer A Count Source Select Register 0                                     *
;*-----------------------------------------------------------------------------*
tacs0		.equ	01D0h
;
tcs0_tacs0		.btequ		0,tacs0		; TA0 count source select bit
tcs1_tacs0		.btequ		1,tacs0		; TA0 count source select bit
tcs2_tacs0		.btequ		2,tacs0		; TA0 count source select bit
tcs3_tacs0		.btequ		3,tacs0		; TA0 count source option specified bit
tcs4_tacs0		.btequ		4,tacs0		; TA1 count source select bit
tcs5_tacs0		.btequ		5,tacs0		; TA1 count source select bit
tcs6_tacs0		.btequ		6,tacs0		; TA1 count source select bit
tcs7_tacs0		.btequ		7,tacs0		; TA1 count source option specified bit
;
;*-----------------------------------------------------------------------------*
;*  Timer A Count Source Select Register 1                                     *
;*-----------------------------------------------------------------------------*
tacs1		.equ	01D1h
;
tcs0_tacs1		.btequ		0,tacs1		; TA2 count source select bit
tcs1_tacs1		.btequ		1,tacs1		; TA2 count source select bit
tcs2_tacs1		.btequ		2,tacs1		; TA2 count source select bit
tcs3_tacs1		.btequ		3,tacs1		; TA2 count source option specified bit
tcs4_tacs1		.btequ		4,tacs1		; TA3 count source select bit
tcs5_tacs1		.btequ		5,tacs1		; TA3 count source select bit
tcs6_tacs1		.btequ		6,tacs1		; TA3 count source select bit
tcs7_tacs1		.btequ		7,tacs1		; TA3 count source option specified bit
;
;*-----------------------------------------------------------------------------*
;*  Timer A Count Source Select Register 2                                     *
;*-----------------------------------------------------------------------------*
tacs2		.equ	01D2h
;
tcs0_tacs2		.btequ		0,tacs2		; TA4 count source select bit
tcs1_tacs2		.btequ		1,tacs2		; TA4 count source select bit
tcs2_tacs2		.btequ		2,tacs2		; TA4 count source select bit
tcs3_tacs2		.btequ		3,tacs2		; TA4 count source option specified bit
;
;*-----------------------------------------------------------------------------*
;*  Timer A Waveform Output Function Select Register                           *
;*-----------------------------------------------------------------------------*
tapofs		.equ	01D5h
;
pofs0			.btequ		0,tapofs	; TA0OUT output polar control bit
pofs1			.btequ		1,tapofs	; TA1OUT output polar control bit
pofs2			.btequ		2,tapofs	; TA2OUT output polar control bit
pofs3			.btequ		3,tapofs	; TA3OUT output polar control bit
pofs4			.btequ		4,tapofs	; TA4OUT output polar control bit
;
;*-----------------------------------------------------------------------------*
;*  Timer B Count Source Select Register 2                                     *
;*-----------------------------------------------------------------------------*
tbcs2		.equ	01E8h
;
tcs0_tbcs2		.btequ		0,tbcs2		; TB3 count source select bit
tcs1_tbcs2		.btequ		1,tbcs2		; TB3 count source select bit
tcs2_tbcs2		.btequ		2,tbcs2		; TB3 count source select bit
tcs3_tbcs2		.btequ		3,tbcs2		; TB3 count source option specified bit
tcs4_tbcs2		.btequ		4,tbcs2		; TB4 count source select bit
tcs5_tbcs2		.btequ		5,tbcs2		; TB4 count source select bit
tcs6_tbcs2		.btequ		6,tbcs2		; TB4 count source select bit
tcs7_tbcs2		.btequ		7,tbcs2		; TB4 count source option specified bit
;
;*-----------------------------------------------------------------------------*
;*  Timer B Count Source Select Register 3                                     *
;*-----------------------------------------------------------------------------*
tbcs3		.equ	01E9h
;
tcs0_tbcs3		.btequ		0,tbcs3		; TB5 count source select bit
tcs1_tbcs3		.btequ		1,tbcs3		; TB5 count source select bit
tcs2_tbcs3		.btequ		2,tbcs3		; TB5 count source select bit
tcs3_tbcs3		.btequ		3,tbcs3		; TB5 count source option specified bit
;
;*-----------------------------------------------------------------------------*
;*  Interrupt Source Select Register 3                                         *
;*-----------------------------------------------------------------------------*
ifsr3a		.equ	0205h
;
ifsr30			.btequ		0,ifsr3a	; INT6~ interrupt polarity select bit
ifsr31			.btequ		1,ifsr3a	; INT7~ interrupt polarity select bit
;
;*-----------------------------------------------------------------------------*
;*  Interrupt Source Select Register 2                                         *
;*-----------------------------------------------------------------------------*
ifsr2a		.equ	0206h
;
ifsr26			.btequ		6,ifsr2a	; Interrupt request source select bit
ifsr27			.btequ		7,ifsr2a	; Interrupt request source select bit
;
;*-----------------------------------------------------------------------------*
;*  Interrupt Source Select Register                                           *
;*-----------------------------------------------------------------------------*
ifsr		.equ	0207h
;
ifsr0			.btequ		0,ifsr		; INT0~ interrupt polarity select bit
ifsr1			.btequ		1,ifsr		; INT1~ interrupt polarity select bit
ifsr2			.btequ		2,ifsr		; INT2~ interrupt polarity select bit
ifsr3			.btequ		3,ifsr		; INT3~ interrupt polarity select bit
ifsr4			.btequ		4,ifsr		; INT4~ interrupt polarity select bit
ifsr5			.btequ		5,ifsr		; INT5~ interrupt polarity select bit
ifsr6			.btequ		6,ifsr		; Interrupt request source select bit
ifsr7			.btequ		7,ifsr		; Interrupt request source select bit
;
;*-----------------------------------------------------------------------------*
;*  Address Match Interrupt Enable Register                                    *
;*-----------------------------------------------------------------------------*
aier		.equ	020Eh
;
aier0			.btequ		0,aier		; Address match interrupt 0 enable bit
aier1			.btequ		1,aier		; Address match interrupt 1 enable bit
;
;*-----------------------------------------------------------------------------*
;*  Address Match Interrupt Enable Register 2                                  *
;*-----------------------------------------------------------------------------*
aier2		.equ	020Fh
;
aier20			.btequ		0,aier2		; Address match interrupt 2 enable bit
aier21			.btequ		1,aier2		; Address match interrupt 3 enable bit
;
;*-----------------------------------------------------------------------------*
;*  Address Match Interrupt Register 0                                         *
;*-----------------------------------------------------------------------------*
rmad0		.equ	0210h
;
rmad0l		.equ	rmad0				; RMAD0 address(low 8bit)
rmad0m		.equ	rmad0+1				; RMAD0 address(mid 8bit)
rmad0h		.equ	rmad0+2				; RMAD0 address(high 8bit)
;
;*-----------------------------------------------------------------------------*
;*  Address Match Interrupt Register 1                                         *
;*-----------------------------------------------------------------------------*
rmad1		.equ	0214h
;
rmad1l		.equ	rmad1				; RMAD1 address(low 8bit)
rmad1m		.equ	rmad1+1				; RMAD1 address(mid 8bit)
rmad1h		.equ	rmad1+2				; RMAD1 address(high 8bit)
;
;*-----------------------------------------------------------------------------*
;*  Address Match Interrupt Register 2                                         *
;*-----------------------------------------------------------------------------*
rmad2		.equ	0218h
;
rmad2l		.equ	rmad2				; RMAD2 address(low 8bit)
rmad2m		.equ	rmad2+1				; RMAD2 address(mid 8bit)
rmad2h		.equ	rmad2+2				; RMAD2 address(high 8bit)
;
;*-----------------------------------------------------------------------------*
;*  Address Match Interrupt Register 3                                         *
;*-----------------------------------------------------------------------------*
rmad3		.equ	021Ch
;
rmad3l		.equ	rmad3				; RMAD3 address(low 8bit)
rmad3m		.equ	rmad3+1				; RMAD3 address(mid 8bit)
rmad3h		.equ	rmad3+2				; RMAD3 address(high 8bit)
;
;*-----------------------------------------------------------------------------*
;*  Flash Memory Control Register 0                                            *
;*-----------------------------------------------------------------------------*
fmr0		.equ	0220h
;
fmr00			.btequ		0,fmr0		; RY/BY~ status flag
fmr01			.btequ		1,fmr0		; CPU rewrite mode select bit
fmr02			.btequ		2,fmr0		; Lock bit disable select bit
fmstp			.btequ		3,fmr0		; Flash memory stop bit
fmr06			.btequ		6,fmr0		; Program status flag
fmr07			.btequ		7,fmr0		; Erase Status Flag
;
;*-----------------------------------------------------------------------------*
;*  Flash Memory Control Register 1                                            *
;*-----------------------------------------------------------------------------*
fmr1		.equ	0221h
;
fmr11			.btequ		1,fmr1		; Write to FMR6 register enable bit
fmr16			.btequ		6,fmr1		; Lock bit status flag
fmr17			.btequ		7,fmr1		; Data flash wait bit
;
;*-----------------------------------------------------------------------------*
;*  Flash Memory Control Register 2                                            *
;*-----------------------------------------------------------------------------*
fmr2		.equ	0222h
;
fmr22			.btequ		2,fmr2		; Slow read mode enable bit
fmr23			.btequ		3,fmr2		; Low-current consumption read mode enable bit
;
;*-----------------------------------------------------------------------------*
;*  Flash Memory Control Register 6                                            *
;*-----------------------------------------------------------------------------*
fmr6		.equ	0230h
;
fmr60			.btequ		0,fmr6		; EW1 mode select bit
fmr61			.btequ		1,fmr6		; Reserved bit
;
;*-----------------------------------------------------------------------------*
;*  UART0 Special Mode Register 4                                              *
;*-----------------------------------------------------------------------------*
u0smr4		.equ	0244h
;
stareq_u0smr4	.btequ		0,u0smr4	; Start condition generate bit
rstareq_u0smr4	.btequ		1,u0smr4	; Restart condition generate bit
stpreq_u0smr4	.btequ		2,u0smr4	; Stop condition generate bit
stspsel_u0smr4	.btequ		3,u0smr4	; SCL, SDA output select bit
ackd_u0smr4		.btequ		4,u0smr4	; ACK data bit
ackc_u0smr4		.btequ		5,u0smr4	; ACK data output enable bit
sclhi_u0smr4	.btequ		6,u0smr4	; SCL output stop enable bit
swc9_u0smr4		.btequ		7,u0smr4	; SCL wait bit 3
;
;*-----------------------------------------------------------------------------*
;*  UART0 Special Mode Register 3                                              *
;*-----------------------------------------------------------------------------*
u0smr3		.equ	0245h
;
ckph_u0smr3		.btequ		1,u0smr3	; Clock phase set bit
nodc_u0smr3		.btequ		3,u0smr3	; Clock output select bit
dl0_u0smr3		.btequ		5,u0smr3	; SDA0 digital delay setup bit
dl1_u0smr3		.btequ		6,u0smr3	; SDA0 digital delay setup bit
dl2_u0smr3		.btequ		7,u0smr3	; SDA0 digital delay setup bit
;
;*-----------------------------------------------------------------------------*
;*  UART0 Special Mode Register 2                                              *
;*-----------------------------------------------------------------------------*
u0smr2		.equ	0246h
;
iicm2_u0smr2	.btequ		0,u0smr2	; I2C mode select bit 2
csc_u0smr2		.btequ		1,u0smr2	; Clock synchronization bit
swc_u0smr2		.btequ		2,u0smr2	; SCL wait output bit
als_u0smr2		.btequ		3,u0smr2	; SDA output stop bit
stac_u0smr2		.btequ		4,u0smr2	; UART0 initialization bit
swc2_u0smr2		.btequ		5,u0smr2	; SCL wait output bit 2
sdhi_u0smr2		.btequ		6,u0smr2	; SDA output disable bit
;
;*-----------------------------------------------------------------------------*
;*  UART0 Special Mode Register                                                *
;*-----------------------------------------------------------------------------*
u0smr		.equ	0247h
;
iicm_u0smr		.btequ		0,u0smr		; I2C mode select bit
abc_u0smr		.btequ		1,u0smr		; Arbitration lost detect flag control bit
bbs_u0smr		.btequ		2,u0smr		; Bus busy flag
abscs_u0smr		.btequ		4,u0smr		; Bus collision detect sampling clock select bit
acse_u0smr		.btequ		5,u0smr		; Auto clear function select bit of transmit enable bit
sss_u0smr		.btequ		6,u0smr		; Transmit start condition select bit
;
;*-----------------------------------------------------------------------------*
;*  UART0 Transmit/Receive Mode Register                                       *
;*-----------------------------------------------------------------------------*
u0mr		.equ	0248h
;
smd0_u0mr		.btequ		0,u0mr		; Serial I/O mode select bit
smd1_u0mr		.btequ		1,u0mr		; Serial I/O mode select bit
smd2_u0mr		.btequ		2,u0mr		; Serial I/O mode select bit
ckdir_u0mr		.btequ		3,u0mr		; Internal/external clock select bit
stps_u0mr		.btequ		4,u0mr		; Stop bit length select bit
pry_u0mr		.btequ		5,u0mr		; Odd/even parity select bit
prye_u0mr		.btequ		6,u0mr		; Parity enable bit
iopol_u0mr		.btequ		7,u0mr		; TXD, RXD I/O polarity reverse bit
;
;*-----------------------------------------------------------------------------*
;*  UART0 Bit Rate Register                                                    *
;*-----------------------------------------------------------------------------*
u0brg		.equ	0249h
;
;*-----------------------------------------------------------------------------*
;*  UART0 Transmit Buffer Register                                             *
;*-----------------------------------------------------------------------------*
u0tb		.equ	024Ah
;
u0tbl		.equ	u0tb				; UART0 Transmit buffer register(low 8bit)
u0tbh		.equ	u0tb+1				; UART0 Transmit buffer register(high 8bit)
;
;*-----------------------------------------------------------------------------*
;*  UART0 Transmit/Receive Control Register 0                                  *
;*-----------------------------------------------------------------------------*
u0c0		.equ	024Ch
;
clk0_u0c0		.btequ		0,u0c0		; U0BRG count source select bit
clk1_u0c0		.btequ		1,u0c0		; U0BRG count source select bit
crs_u0c0		.btequ		2,u0c0		; CTS~/RTS~ function select bit
txept_u0c0		.btequ		3,u0c0		; Transmit register empty flag
crd_u0c0		.btequ		4,u0c0		; CTS~/RTS~ disable bit
nch_u0c0		.btequ		5,u0c0		; Data output select bit
ckpol_u0c0		.btequ		6,u0c0		; CLK polarity select bit
uform_u0c0		.btequ		7,u0c0		; Transfer format select bit
;
;*-----------------------------------------------------------------------------*
;*  UART0 Transmit/Receive Control Register 1                                  *
;*-----------------------------------------------------------------------------*
u0c1		.equ	024Dh
;
te_u0c1			.btequ		0,u0c1		; Transmit enable bit
ti_u0c1			.btequ		1,u0c1		; Transmit buffer empty flag
re_u0c1			.btequ		2,u0c1		; Receive enable bit
ri_u0c1			.btequ		3,u0c1		; Receive complete flag
u0lch			.btequ		6,u0c1		; Data logic select bit
u0ere			.btequ		7,u0c1		; Error signal output enable bit
;
;*-----------------------------------------------------------------------------*
;*  UART0 Receive Buffer Register                                              *
;*-----------------------------------------------------------------------------*
u0rb		.equ	024Eh
;
u0rbl		.equ	u0rb				; UART0 receive buffer register(low 8bit)
u0rbh		.equ	u0rb+1				; UART0 receive buffer register(high 8bit)
;
abt_u0rb		.btequ		11,u0rb		; Arbitration lost detect flag
oer_u0rb		.btequ		12,u0rb		; Overrun error flag
fer_u0rb		.btequ		13,u0rb		; Framing error flag
per_u0rb		.btequ		14,u0rb		; Parity error flag
sum_u0rb		.btequ		15,u0rb		; Error sum flag
;
;*-----------------------------------------------------------------------------*
;*  UART Transmit/Receive Control Register 2                                   *
;*-----------------------------------------------------------------------------*
ucon		.equ	0250h
;
u0irs			.btequ		0,ucon		; UART0 transmit interrupt source select bit
u1irs			.btequ		1,ucon		; UART1 transmit interrupt source select bit
u0rrm			.btequ		2,ucon		; UART0 continuous receive mode enable bit
u1rrm			.btequ		3,ucon		; UART1 continuous receive mode enable bit
clkmd0			.btequ		4,ucon		; UART1 CLK, CLKS select bit 0
clkmd1			.btequ		5,ucon		; UART1 CLK, CLKS select bit 1
rcsp			.btequ		6,ucon		; Separate UART0 CTS~/RTS~ bit
;
;*-----------------------------------------------------------------------------*
;*  UART1 Special Mode Register 4                                              *
;*-----------------------------------------------------------------------------*
u1smr4		.equ	0254h
;
stareq_u1smr4	.btequ		0,u1smr4	; Start condition generate bit
rstareq_u1smr4	.btequ		1,u1smr4	; Restart condition generate bit
stpreq_u1smr4	.btequ		2,u1smr4	; Stop condition generate bit
stspsel_u1smr4	.btequ		3,u1smr4	; SCL, SDA output select bit
ackd_u1smr4		.btequ		4,u1smr4	; ACK data bit
ackc_u1smr4		.btequ		5,u1smr4	; ACK data output enable bit
sclhi_u1smr4	.btequ		6,u1smr4	; SCL output stop enable bit
swc9_u1smr4		.btequ		7,u1smr4	; SCL wait bit 3
;
;*-----------------------------------------------------------------------------*
;*  UART1 Special Mode Register 3                                              *
;*-----------------------------------------------------------------------------*
u1smr3		.equ	0255h
;
ckph_u1smr3		.btequ		1,u1smr3	; Clock phase set bit
nodc_u1smr3		.btequ		3,u1smr3	; Clock output select bit
dl0_u1smr3		.btequ		5,u1smr3	; SDA1 digital delay setup bit
dl1_u1smr3		.btequ		6,u1smr3	; SDA1 digital delay setup bit
dl2_u1smr3		.btequ		7,u1smr3	; SDA1 digital delay setup bit
;
;*-----------------------------------------------------------------------------*
;*  UART1 Special Mode Register 2                                              *
;*-----------------------------------------------------------------------------*
u1smr2		.equ	0256h
;
iicm2_u1smr2	.btequ		0,u1smr2	; I2C mode select bit 2
csc_u1smr2		.btequ		1,u1smr2	; Clock synchronization bit
swc_u1smr2		.btequ		2,u1smr2	; SCL wait output bit
als_u1smr2		.btequ		3,u1smr2	; SDA output stop bit
stac_u1smr2		.btequ		4,u1smr2	; UART1 initialization bit
swc2_u1smr2		.btequ		5,u1smr2	; SCL wait output bit 2
sdhi_u1smr2		.btequ		6,u1smr2	; SDA output disable bit
;
;*-----------------------------------------------------------------------------*
;*  UART1 Special Mode Register                                                *
;*-----------------------------------------------------------------------------*
u1smr		.equ	0257h
;
iicm_u1smr		.btequ		0,u1smr		; I2C mode select bit
abc_u1smr		.btequ		1,u1smr		; Arbitration lost detect flag control bit
bbs_u1smr		.btequ		2,u1smr		; Bus busy flag
abscs_u1smr		.btequ		4,u1smr		; Bus collision detect sampling clock select bit
acse_u1smr		.btequ		5,u1smr		; Auto clear function select bit of transmit enable bit
sss_u1smr		.btequ		6,u1smr		; Transmit start condition select bit
;
;*-----------------------------------------------------------------------------*
;*  UART1 Transmit/Receive Mode Register                                       *
;*-----------------------------------------------------------------------------*
u1mr		.equ	0258h
;
smd0_u1mr		.btequ		0,u1mr		; Serial I/O mode select bit
smd1_u1mr		.btequ		1,u1mr		; Serial I/O mode select bit
smd2_u1mr		.btequ		2,u1mr		; Serial I/O mode select bit
ckdir_u1mr		.btequ		3,u1mr		; Internal/external clock select bit
stps_u1mr		.btequ		4,u1mr		; Stop bit length select bit
pry_u1mr		.btequ		5,u1mr		; Odd/even parity select bit
prye_u1mr		.btequ		6,u1mr		; Parity enable bit
iopol_u1mr		.btequ		7,u1mr		; TXD, RXD I/O polarity reverse bit
;
;*-----------------------------------------------------------------------------*
;*  UART1 Bit Rate Register                                                    *
;*-----------------------------------------------------------------------------*
u1brg		.equ	0259h
;
;*-----------------------------------------------------------------------------*
;*  UART1 Transmit Buffer Register                                             *
;*-----------------------------------------------------------------------------*
u1tb		.equ	025Ah
;
u1tbl		.equ	u1tb				; UART1 Transmit buffer register(low 8bit)
u1tbh		.equ	u1tb+1				; UART1 Transmit buffer register(high 8bit)
;
;*-----------------------------------------------------------------------------*
;*  UART1 Transmit/Receive Control Register 0                                  *
;*-----------------------------------------------------------------------------*
u1c0		.equ	025Ch
;
clk0_u1c0		.btequ		0,u1c0		; U1BRG count source select bit
clk1_u1c0		.btequ		1,u1c0		; U1BRG count source select bit
crs_u1c0		.btequ		2,u1c0		; CTS~/RTS~ function select bit
txept_u1c0		.btequ		3,u1c0		; Transmit register empty flag
crd_u1c0		.btequ		4,u1c0		; CTS~/RTS~ disable bit
nch_u1c0		.btequ		5,u1c0		; Data output select bit
ckpol_u1c0		.btequ		6,u1c0		; CLK polarity select bit
uform_u1c0		.btequ		7,u1c0		; Transfer format select bit
;
;*-----------------------------------------------------------------------------*
;*  UART1 Transmit/Receive Control Register 1                                  *
;*-----------------------------------------------------------------------------*
u1c1		.equ	025Dh
;
te_u1c1			.btequ		0,u1c1		; Transmit enable bit
ti_u1c1			.btequ		1,u1c1		; Transmit buffer empty flag
re_u1c1			.btequ		2,u1c1		; Receive enable bit
ri_u1c1			.btequ		3,u1c1		; Receive complete flag
u1lch			.btequ		6,u1c1		; Data logic select bit
u1ere			.btequ		7,u1c1		; Error signal output enable bit
;
;*-----------------------------------------------------------------------------*
;*  UART1 Receive Buffer Register                                              *
;*-----------------------------------------------------------------------------*
u1rb		.equ	025Eh
;
u1rbl		.equ	u1rb				; UART1 receive buffer register(low 8bit)
u1rbh		.equ	u1rb+1				; UART1 receive buffer register(high 8bit)
;
abt_u1rb		.btequ		11,u1rb		; Arbitration lost detect flag
oer_u1rb		.btequ		12,u1rb		; Overrun error flag
fer_u1rb		.btequ		13,u1rb		; Framing error flag
per_u1rb		.btequ		14,u1rb		; Parity error flag
sum_u1rb		.btequ		15,u1rb		; Error sum flag
;
;*-----------------------------------------------------------------------------*
;*  UART2 Special Mode Register 4                                              *
;*-----------------------------------------------------------------------------*
u2smr4		.equ	0264h
;
stareq_u2smr4	.btequ		0,u2smr4	; Start condition generate bit
rstareq_u2smr4	.btequ		1,u2smr4	; Restart condition generate bit
stpreq_u2smr4	.btequ		2,u2smr4	; Stop condition generate bit
stspsel_u2smr4	.btequ		3,u2smr4	; SCL, SDA output select bit
ackd_u2smr4		.btequ		4,u2smr4	; ACK data bit
ackc_u2smr4		.btequ		5,u2smr4	; ACK data output enable bit
sclhi_u2smr4	.btequ		6,u2smr4	; SCL output stop enable bit
swc9_u2smr4		.btequ		7,u2smr4	; SCL wait bit 3
;
;*-----------------------------------------------------------------------------*
;*  UART2 Special Mode Register 3                                              *
;*-----------------------------------------------------------------------------*
u2smr3		.equ	0265h
;
ckph_u2smr3		.btequ		1,u2smr3	; Clock phase set bit
nodc_u2smr3		.btequ		3,u2smr3	; Clock output select bit
dl0_u2smr3		.btequ		5,u2smr3	; SDA2 digital delay setup bit
dl1_u2smr3		.btequ		6,u2smr3	; SDA2 digital delay setup bit
dl2_u2smr3		.btequ		7,u2smr3	; SDA2 digital delay setup bit
;
;*-----------------------------------------------------------------------------*
;*  UART2 Special Mode Register 2                                              *
;*-----------------------------------------------------------------------------*
u2smr2		.equ	0266h
;
iicm2_u2smr2	.btequ		0,u2smr2	; I2C mode select bit 2
csc_u2smr2		.btequ		1,u2smr2	; Clock synchronization bit
swc_u2smr2		.btequ		2,u2smr2	; SCL wait output bit
als_u2smr2		.btequ		3,u2smr2	; SDA output stop bit
stac_u2smr2		.btequ		4,u2smr2	; UART2 initialization bit
swc2_u2smr2		.btequ		5,u2smr2	; SCL wait output bit 2
sdhi_u2smr2		.btequ		6,u2smr2	; SDA output disable bit
;
;*-----------------------------------------------------------------------------*
;*  UART2 Special Mode Register                                                *
;*-----------------------------------------------------------------------------*
u2smr		.equ	0267h
;
iicm_u2smr		.btequ		0,u2smr		; I2C mode select bit
abc_u2smr		.btequ		1,u2smr		; Arbitration lost detect flag control bit
bbs_u2smr		.btequ		2,u2smr		; Bus busy flag
abscs_u2smr		.btequ		4,u2smr		; Bus collision detect sampling clock select bit
acse_u2smr		.btequ		5,u2smr		; Auto clear function select bit of transmit enable bit
sss_u2smr		.btequ		6,u2smr		; Transmit start condition select bit
;
;*-----------------------------------------------------------------------------*
;*  UART2 Transmit/Receive Mode Register                                       *
;*-----------------------------------------------------------------------------*
u2mr		.equ	0268h
;
smd0_u2mr		.btequ		0,u2mr		; Serial I/O mode select bit
smd1_u2mr		.btequ		1,u2mr		; Serial I/O mode select bit
smd2_u2mr		.btequ		2,u2mr		; Serial I/O mode select bit
ckdir_u2mr		.btequ		3,u2mr		; Internal/external clock select bit
stps_u2mr		.btequ		4,u2mr		; Stop bit length select bit
pry_u2mr		.btequ		5,u2mr		; Odd/even parity select bit
prye_u2mr		.btequ		6,u2mr		; Parity enable bit
iopol_u2mr		.btequ		7,u2mr		; TXD, RXD I/O polarity reverse bit
;
;*-----------------------------------------------------------------------------*
;*  UART2 Bit Rate Register                                                    *
;*-----------------------------------------------------------------------------*
u2brg		.equ	0269h
;
;*-----------------------------------------------------------------------------*
;*  UART2 Transmit Buffer Register                                             *
;*-----------------------------------------------------------------------------*
u2tb		.equ	026Ah
;
u2tbl		.equ	u2tb				; UART2 Transmit buffer register(low 8bit)
u2tbh		.equ	u2tb+1				; UART2 Transmit buffer register(high 8bit)
;
;*-----------------------------------------------------------------------------*
;*  UART2 Transmit/Receive Control Register 0                                  *
;*-----------------------------------------------------------------------------*
u2c0		.equ	026Ch
;
clk0_u2c0		.btequ		0,u2c0		; U2BRG count source select bit
clk1_u2c0		.btequ		1,u2c0		; U2BRG count source select bit
crs_u2c0		.btequ		2,u2c0		; CTS~/RTS~ function select bit
txept_u2c0		.btequ		3,u2c0		; Transmit register empty flag
crd_u2c0		.btequ		4,u2c0		; CTS~/RTS~ disable bit
nch_u2c0		.btequ		5,u2c0		; Data output select bit
ckpol_u2c0		.btequ		6,u2c0		; CLK polarity select bit
uform_u2c0		.btequ		7,u2c0		; Transfer format select bit
;
;*-----------------------------------------------------------------------------*
;*  UART2 Transmit/Receive Control Register 1                                  *
;*-----------------------------------------------------------------------------*
u2c1		.equ	026Dh
;
te_u2c1			.btequ		0,u2c1		; Transmit enable bit
ti_u2c1			.btequ		1,u2c1		; Transmit buffer empty flag
re_u2c1			.btequ		2,u2c1		; Receive enable bit
ri_u2c1			.btequ		3,u2c1		; Receive complete flag
u2irs			.btequ		4,u2c1		; UART2 transmit interrupt source select bit
u2rrm			.btequ		5,u2c1		; UART2 continuous receive mode enable bit
u2lch			.btequ		6,u2c1		; Data logic select bit
u2ere			.btequ		7,u2c1		; Error signal output enable bit
;
;*-----------------------------------------------------------------------------*
;*  UART2 Receive Buffer Register                                              *
;*-----------------------------------------------------------------------------*
u2rb		.equ	026Eh
;
u2rbl		.equ	u2rb				; UART2 receive buffer register(low 8bit)
u2rbh		.equ	u2rb+1				; UART2 receive buffer register(high 8bit)
;
abt_u2rb		.btequ		11,u2rb		; Arbitration lost detect flag
oer_u2rb		.btequ		12,u2rb		; Overrun error flag
fer_u2rb		.btequ		13,u2rb		; Framing error flag
per_u2rb		.btequ		14,u2rb		; Parity error flag
sum_u2rb		.btequ		15,u2rb		; Error sum flag
;
;*-----------------------------------------------------------------------------*
;*  SI/O3 Transmit/Receive Register                                            *
;*-----------------------------------------------------------------------------*
s3trr		.equ	0270h
;
;*-----------------------------------------------------------------------------*
;*  SI/O3 Control Register                                                     *
;*-----------------------------------------------------------------------------*
s3c			.equ	0272h
;
sm30			.btequ		0,s3c		; Internal synchronous clock select bit
sm31			.btequ		1,s3c		; Internal synchronous clock select bit
sm32			.btequ		2,s3c		; SOUT3 output disable bit
sm33			.btequ		3,s3c		; SI/O3 port select bit
sm34			.btequ		4,s3c		; CLK polarity select bit
sm35			.btequ		5,s3c		; Transfer direction select bit
sm36			.btequ		6,s3c		; Synchronous clock select bit
sm37			.btequ		7,s3c		; SOUT3 initial value set bit
;
;*-----------------------------------------------------------------------------*
;*  SI/O3 Bit Rate Register                                                    *
;*-----------------------------------------------------------------------------*
s3brg		.equ	0273h
;
;*-----------------------------------------------------------------------------*
;*  SI/O4 Transmit/Receive Register                                            *
;*-----------------------------------------------------------------------------*
s4trr		.equ	0274h
;
;*-----------------------------------------------------------------------------*
;*  SI/O4 Control Register                                                     *
;*-----------------------------------------------------------------------------*
s4c			.equ	0276h
;
sm40			.btequ		0,s4c		; Internal synchronous clock select bit
sm41			.btequ		1,s4c		; Internal synchronous clock select bit
sm42			.btequ		2,s4c		; SOUT4 output disable bit
sm43			.btequ		3,s4c		; SI/O4 port select bit
sm44			.btequ		4,s4c		; CLK polarity select bit
sm45			.btequ		5,s4c		; Transfer direction select bit
sm46			.btequ		6,s4c		; Synchronous clock select bit
sm47			.btequ		7,s4c		; SOUT4 initial value set bit
;
;*-----------------------------------------------------------------------------*
;*  SI/O4 Bit Rate Register                                                    *
;*-----------------------------------------------------------------------------*
s4brg		.equ	0277h
;
;*-----------------------------------------------------------------------------*
;*  SI/O34 Control Register 2                                                  *
;*-----------------------------------------------------------------------------*
s34c2		.equ	0278h
;
sm26			.btequ		6,s34c2		; SOUT3 output control bit
sm27			.btequ		7,s34c2		; SOUT4 output control bit
;
;*-----------------------------------------------------------------------------*
;*  UART5 Special Mode Register 4                                              *
;*-----------------------------------------------------------------------------*
u5smr4		.equ	0284h
;
stareq_u5smr4	.btequ		0,u5smr4	; Start condition generate bit
rstareq_u5smr4	.btequ		1,u5smr4	; Restart condition generate bit
stpreq_u5smr4	.btequ		2,u5smr4	; Stop condition generate bit
stspsel_u5smr4	.btequ		3,u5smr4	; SCL, SDA output select bit
ackd_u5smr4		.btequ		4,u5smr4	; ACK data bit
ackc_u5smr4		.btequ		5,u5smr4	; ACK data output enable bit
sclhi_u5smr4	.btequ		6,u5smr4	; SCL output stop enable bit
swc9_u5smr4		.btequ		7,u5smr4	; SCL wait bit 3
;
;*-----------------------------------------------------------------------------*
;*  UART5 Special Mode Register 3                                              *
;*-----------------------------------------------------------------------------*
u5smr3		.equ	0285h
;
ckph_u5smr3		.btequ		1,u5smr3	; Clock phase set bit
nodc_u5smr3		.btequ		3,u5smr3	; Clock output select bit
dl0_u5smr3		.btequ		5,u5smr3	; SDA5 digital delay setup bit
dl1_u5smr3		.btequ		6,u5smr3	; SDA5 digital delay setup bit
dl2_u5smr3		.btequ		7,u5smr3	; SDA5 digital delay setup bit
;
;*-----------------------------------------------------------------------------*
;*  UART5 Special Mode Register 2                                              *
;*-----------------------------------------------------------------------------*
u5smr2		.equ	0286h
;
iicm2_u5smr2	.btequ		0,u5smr2	; I2C mode select bit 2
csc_u5smr2		.btequ		1,u5smr2	; Clock synchronization bit
swc_u5smr2		.btequ		2,u5smr2	; SCL wait output bit
als_u5smr2		.btequ		3,u5smr2	; SDA output stop bit
stac_u5smr2		.btequ		4,u5smr2	; UART5 initialization bit
swc2_u5smr2		.btequ		5,u5smr2	; SCL wait output bit 2
sdhi_u5smr2		.btequ		6,u5smr2	; SDA output disable bit
;
;*-----------------------------------------------------------------------------*
;*  UART5 Special Mode Register                                                *
;*-----------------------------------------------------------------------------*
u5smr		.equ	0287h
;
iicm_u5smr		.btequ		0,u5smr		; I2C mode select bit
abc_u5smr		.btequ		1,u5smr		; Arbitration lost detect flag control bit
bbs_u5smr		.btequ		2,u5smr		; Bus busy flag
abscs_u5smr		.btequ		4,u5smr		; Bus collision detect sampling clock select bit
acse_u5smr		.btequ		5,u5smr		; Auto clear function select bit of transmit enable bit
sss_u5smr		.btequ		6,u5smr		; Transmit start condition select bit
;
;*-----------------------------------------------------------------------------*
;*  UART5 Transmit/Receive Mode Register                                       *
;*-----------------------------------------------------------------------------*
u5mr		.equ	0288h
;
smd0_u5mr		.btequ		0,u5mr		; Serial I/O mode select bit
smd1_u5mr		.btequ		1,u5mr		; Serial I/O mode select bit
smd2_u5mr		.btequ		2,u5mr		; Serial I/O mode select bit
ckdir_u5mr		.btequ		3,u5mr		; Internal/external clock select bit
stps_u5mr		.btequ		4,u5mr		; Stop bit length select bit
pry_u5mr		.btequ		5,u5mr		; Odd/even parity select bit
prye_u5mr		.btequ		6,u5mr		; Parity enable bit
iopol_u5mr		.btequ		7,u5mr		; TXD, RXD I/O polarity reverse bit
;
;*-----------------------------------------------------------------------------*
;*  UART5 Bit Rate Register                                                    *
;*-----------------------------------------------------------------------------*
u5brg		.equ	0289h
;
;*-----------------------------------------------------------------------------*
;*  UART5 Transmit Buffer Register                                             *
;*-----------------------------------------------------------------------------*
u5tb		.equ	028Ah
;
u5tbl		.equ	u5tb				; UART5 Transmit buffer register(low 8bit)
u5tbh		.equ	u5tb+1				; UART5 Transmit buffer register(high 8bit)
;
;*-----------------------------------------------------------------------------*
;*  UART5 Transmit/Receive Control Register 0                                  *
;*-----------------------------------------------------------------------------*
u5c0		.equ	028Ch
;
clk0_u5c0		.btequ		0,u5c0		; U5BRG count source select bit
clk1_u5c0		.btequ		1,u5c0		; U5BRG count source select bit
crs_u5c0		.btequ		2,u5c0		; CTS~/RTS~ function select bit
txept_u5c0		.btequ		3,u5c0		; Transmit register empty flag
crd_u5c0		.btequ		4,u5c0		; CTS~/RTS~ disable bit
nch_u5c0		.btequ		5,u5c0		; Data output select bit
ckpol_u5c0		.btequ		6,u5c0		; CLK polarity select bit
uform_u5c0		.btequ		7,u5c0		; Transfer format select bit
;
;*-----------------------------------------------------------------------------*
;*  UART5 Transmit/Receive Control Register 1                                  *
;*-----------------------------------------------------------------------------*
u5c1		.equ	028Dh
;
te_u5c1			.btequ		0,u5c1		; Transmit enable bit
ti_u5c1			.btequ		1,u5c1		; Transmit buffer empty flag
re_u5c1			.btequ		2,u5c1		; Receive enable bit
ri_u5c1			.btequ		3,u5c1		; Receive complete flag
u5irs			.btequ		4,u5c1		; UART5 transmit interrupt source select bit
u5rrm			.btequ		5,u5c1		; UART5 continuous receive mode enable bit
u5lch			.btequ		6,u5c1		; Data logic select bit
u5ere			.btequ		7,u5c1		; Error signal output enable bit
;
;*-----------------------------------------------------------------------------*
;*  UART5 Receive Buffer Register                                              *
;*-----------------------------------------------------------------------------*
u5rb		.equ	028Eh
;
u5rbl		.equ	u5rb				; UART5 receive buffer register(low 8bit)
u5rbh		.equ	u5rb+1				; UART5 receive buffer register(high 8bit)
;
abt_u5rb		.btequ		11,u5rb		; Arbitration lost detect flag
oer_u5rb		.btequ		12,u5rb		; Overrun error flag
fer_u5rb		.btequ		13,u5rb		; Framing error flag
per_u5rb		.btequ		14,u5rb		; Parity error flag
sum_u5rb		.btequ		15,u5rb		; Error sum flag
;
;*-----------------------------------------------------------------------------*
;*  UART6 Special Mode Register 4                                              *
;*-----------------------------------------------------------------------------*
u6smr4		.equ	0294h
;
stareq_u6smr4	.btequ		0,u6smr4	; Start condition generate bit
rstareq_u6smr4	.btequ		1,u6smr4	; Restart condition generate bit
stpreq_u6smr4	.btequ		2,u6smr4	; Stop condition generate bit
stspsel_u6smr4	.btequ		3,u6smr4	; SCL, SDA output select bit
ackd_u6smr4		.btequ		4,u6smr4	; ACK data bit
ackc_u6smr4		.btequ		5,u6smr4	; ACK data output enable bit
sclhi_u6smr4	.btequ		6,u6smr4	; SCL output stop enable bit
swc9_u6smr4		.btequ		7,u6smr4	; SCL wait bit 3
;
;*-----------------------------------------------------------------------------*
;*  UART6 Special Mode Register 3                                              *
;*-----------------------------------------------------------------------------*
u6smr3		.equ	0295h
;
ckph_u6smr3		.btequ		1,u6smr3	; Clock phase set bit
nodc_u6smr3		.btequ		3,u6smr3	; Clock output select bit
dl0_u6smr3		.btequ		5,u6smr3	; SDA6 digital delay setup bit
dl1_u6smr3		.btequ		6,u6smr3	; SDA6 digital delay setup bit
dl2_u6smr3		.btequ		7,u6smr3	; SDA6 digital delay setup bit
;
;*-----------------------------------------------------------------------------*
;*  UART6 Special Mode Register 2                                              *
;*-----------------------------------------------------------------------------*
u6smr2		.equ	0296h
;
iicm2_u6smr2	.btequ		0,u6smr2	; I2C mode select bit 2
csc_u6smr2		.btequ		1,u6smr2	; Clock synchronization bit
swc_u6smr2		.btequ		2,u6smr2	; SCL wait output bit
als_u6smr2		.btequ		3,u6smr2	; SDA output stop bit
stac_u6smr2		.btequ		4,u6smr2	; UART6 initialization bit
swc2_u6smr2		.btequ		5,u6smr2	; SCL wait output bit 2
sdhi_u6smr2		.btequ		6,u6smr2	; SDA output disable bit
;
;*-----------------------------------------------------------------------------*
;*  UART6 Special Mode Register                                                *
;*-----------------------------------------------------------------------------*
u6smr		.equ	0297h
;
iicm_u6smr		.btequ		0,u6smr		; I2C mode select bit
abc_u6smr		.btequ		1,u6smr		; Arbitration lost detect flag control bit
bbs_u6smr		.btequ		2,u6smr		; Bus busy flag
abscs_u6smr		.btequ		4,u6smr		; Bus collision detect sampling clock select bit
acse_u6smr		.btequ		5,u6smr		; Auto clear function select bit of transmit enable bit
sss_u6smr		.btequ		6,u6smr		; Transmit start condition select bit
;
;*-----------------------------------------------------------------------------*
;*  UART6 Transmit/Receive Mode Register                                       *
;*-----------------------------------------------------------------------------*
u6mr		.equ	0298h
;
smd0_u6mr		.btequ		0,u6mr		; Serial I/O mode select bit
smd1_u6mr		.btequ		1,u6mr		; Serial I/O mode select bit
smd2_u6mr		.btequ		2,u6mr		; Serial I/O mode select bit
ckdir_u6mr		.btequ		3,u6mr		; Internal/external clock select bit
stps_u6mr		.btequ		4,u6mr		; Stop bit length select bit
pry_u6mr		.btequ		5,u6mr		; Odd/even parity select bit
prye_u6mr		.btequ		6,u6mr		; Parity enable bit
iopol_u6mr		.btequ		7,u6mr		; TXD, RXD I/O polarity reverse bit
;
;*-----------------------------------------------------------------------------*
;*  UART6 Bit Rate Register                                                    *
;*-----------------------------------------------------------------------------*
u6brg		.equ	0299h
;
;*-----------------------------------------------------------------------------*
;*  UART6 Transmit Buffer Register                                             *
;*-----------------------------------------------------------------------------*
u6tb		.equ	029Ah
;
u6tbl		.equ	u6tb				; UART6 Transmit buffer register(low 8bit)
u6tbh		.equ	u6tb+1				; UART6 Transmit buffer register(high 8bit)
;
;*-----------------------------------------------------------------------------*
;*  UART6 Transmit/Receive Control Register 0                                  *
;*-----------------------------------------------------------------------------*
u6c0		.equ	029Ch
;
clk0_u6c0		.btequ		0,u6c0		; U6BRG count source select bit
clk1_u6c0		.btequ		1,u6c0		; U6BRG count source select bit
crs_u6c0		.btequ		2,u6c0		; CTS~/RTS~ function select bit
txept_u6c0		.btequ		3,u6c0		; Transmit register empty flag
crd_u6c0		.btequ		4,u6c0		; CTS~/RTS~ disable bit
nch_u6c0		.btequ		5,u6c0		; Data output select bit
ckpol_u6c0		.btequ		6,u6c0		; CLK polarity select bit
uform_u6c0		.btequ		7,u6c0		; Transfer format select bit
;
;*-----------------------------------------------------------------------------*
;*  UART6 Transmit/Receive Control Register 1                                  *
;*-----------------------------------------------------------------------------*
u6c1		.equ	029Dh
;
te_u6c1			.btequ		0,u6c1		; Transmit enable bit
ti_u6c1			.btequ		1,u6c1		; Transmit buffer empty flag
re_u6c1			.btequ		2,u6c1		; Receive enable bit
ri_u6c1			.btequ		3,u6c1		; Receive complete flag
u6irs			.btequ		4,u6c1		; UART6 transmit interrupt source select bit
u6rrm			.btequ		5,u6c1		; UART6 continuous receive mode enable bit
u6lch			.btequ		6,u6c1		; Data logic select bit
u6ere			.btequ		7,u6c1		; Error signal output enable bit
;
;*-----------------------------------------------------------------------------*
;*  UART6 Receive Buffer Register                                              *
;*-----------------------------------------------------------------------------*
u6rb		.equ	029Eh
;
u6rbl		.equ	u6rb				; UART6 receive buffer register(low 8bit)
u6rbh		.equ	u6rb+1				; UART6 receive buffer register(high 8bit)
;
abt_u6rb		.btequ		11,u6rb		; Arbitration lost detect flag
oer_u6rb		.btequ		12,u6rb		; Overrun error flag
fer_u6rb		.btequ		13,u6rb		; Framing error flag
per_u6rb		.btequ		14,u6rb		; Parity error flag
sum_u6rb		.btequ		15,u6rb		; Error sum flag
;
;*-----------------------------------------------------------------------------*
;*  UART7 Special Mode Register 4                                              *
;*-----------------------------------------------------------------------------*
u7smr4		.equ	02A4h
;
stareq_u7smr4	.btequ		0,u7smr4	; Start condition generate bit
rstareq_u7smr4	.btequ		1,u7smr4	; Restart condition generate bit
stpreq_u7smr4	.btequ		2,u7smr4	; Stop condition generate bit
stspsel_u7smr4	.btequ		3,u7smr4	; SCL, SDA output select bit
ackd_u7smr4		.btequ		4,u7smr4	; ACK data bit
ackc_u7smr4		.btequ		5,u7smr4	; ACK data output enable bit
sclhi_u7smr4	.btequ		6,u7smr4	; SCL output stop enable bit
swc9_u7smr4		.btequ		7,u7smr4	; SCL wait bit 3
;
;*-----------------------------------------------------------------------------*
;*  UART7 Special Mode Register 3                                              *
;*-----------------------------------------------------------------------------*
u7smr3		.equ	02A5h
;
ckph_u7smr3		.btequ		1,u7smr3	; Clock phase set bit
nodc_u7smr3		.btequ		3,u7smr3	; Clock output select bit
dl0_u7smr3		.btequ		5,u7smr3	; SDA7 digital delay setup bit
dl1_u7smr3		.btequ		6,u7smr3	; SDA7 digital delay setup bit
dl2_u7smr3		.btequ		7,u7smr3	; SDA7 digital delay setup bit
;
;*-----------------------------------------------------------------------------*
;*  UART7 Special Mode Register 2                                              *
;*-----------------------------------------------------------------------------*
u7smr2		.equ	02A6h
;
iicm2_u7smr2	.btequ		0,u7smr2	; I2C mode select bit 2
csc_u7smr2		.btequ		1,u7smr2	; Clock synchronization bit
swc_u7smr2		.btequ		2,u7smr2	; SCL wait output bit
als_u7smr2		.btequ		3,u7smr2	; SDA output stop bit
stac_u7smr2		.btequ		4,u7smr2	; UART7 initialization bit
swc2_u7smr2		.btequ		5,u7smr2	; SCL wait output bit 2
sdhi_u7smr2		.btequ		6,u7smr2	; SDA output disable bit
;
;*-----------------------------------------------------------------------------*
;*  UART7 Special Mode Register                                                *
;*-----------------------------------------------------------------------------*
u7smr		.equ	02A7h
;
iicm_u7smr		.btequ		0,u7smr		; I2C mode select bit
abc_u7smr		.btequ		1,u7smr		; Arbitration lost detect flag control bit
bbs_u7smr		.btequ		2,u7smr		; Bus busy flag
abscs_u7smr		.btequ		4,u7smr		; Bus collision detect sampling clock select bit
acse_u7smr		.btequ		5,u7smr		; Auto clear function select bit of transmit enable bit
sss_u7smr		.btequ		6,u7smr		; Transmit start condition select bit
;
;*-----------------------------------------------------------------------------*
;*  UART7 Transmit/Receive Mode Register                                       *
;*-----------------------------------------------------------------------------*
u7mr		.equ	02A8h
;
smd0_u7mr		.btequ		0,u7mr		; Serial I/O mode select bit
smd1_u7mr		.btequ		1,u7mr		; Serial I/O mode select bit
smd2_u7mr		.btequ		2,u7mr		; Serial I/O mode select bit
ckdir_u7mr		.btequ		3,u7mr		; Internal/external clock select bit
stps_u7mr		.btequ		4,u7mr		; Stop bit length select bit
pry_u7mr		.btequ		5,u7mr		; Odd/even parity select bit
prye_u7mr		.btequ		6,u7mr		; Parity enable bit
iopol_u7mr		.btequ		7,u7mr		; TXD, RXD I/O polarity reverse bit
;
;*-----------------------------------------------------------------------------*
;*  UART7 Bit Rate Register                                                    *
;*-----------------------------------------------------------------------------*
u7brg		.equ	02A9h
;
;*-----------------------------------------------------------------------------*
;*  UART7 Transmit Buffer Register                                             *
;*-----------------------------------------------------------------------------*
u7tb		.equ	02AAh
;
u7tbl		.equ	u7tb				; UART7 Transmit buffer register(low 8bit)
u7tbh		.equ	u7tb+1				; UART7 Transmit buffer register(high 8bit)
;
;*-----------------------------------------------------------------------------*
;*  UART7 Transmit/Receive Control Register 0                                  *
;*-----------------------------------------------------------------------------*
u7c0		.equ	02ACh
;
clk0_u7c0		.btequ		0,u7c0		; U7BRG count source select bit
clk1_u7c0		.btequ		1,u7c0		; U7BRG count source select bit
crs_u7c0		.btequ		2,u7c0		; CTS~/RTS~ function select bit
txept_u7c0		.btequ		3,u7c0		; Transmit register empty flag
crd_u7c0		.btequ		4,u7c0		; CTS~/RTS~ disable bit
nch_u7c0		.btequ		5,u7c0		; Data output select bit
ckpol_u7c0		.btequ		6,u7c0		; CLK polarity select bit
uform_u7c0		.btequ		7,u7c0		; Transfer format select bit
;
;*-----------------------------------------------------------------------------*
;*  UART7 Transmit/Receive Control Register 1                                  *
;*-----------------------------------------------------------------------------*
u7c1		.equ	02ADh
;
te_u7c1			.btequ		0,u7c1		; Transmit enable bit
ti_u7c1			.btequ		1,u7c1		; Transmit buffer empty flag
re_u7c1			.btequ		2,u7c1		; Receive enable bit
ri_u7c1			.btequ		3,u7c1		; Receive complete flag
u7irs			.btequ		4,u7c1		; UART7 transmit interrupt source select bit
u7rrm			.btequ		5,u7c1		; UART7 continuous receive mode enable bit
u7lch			.btequ		6,u7c1		; Data logic select bit
u7ere			.btequ		7,u7c1		; Error signal output enable bit
;
;*-----------------------------------------------------------------------------*
;*  UART7 Receive Buffer Register                                              *
;*-----------------------------------------------------------------------------*
u7rb		.equ	02AEh
;
u7rbl		.equ	u7rb				; UART7 receive buffer register(low 8bit)
u7rbh		.equ	u7rb+1				; UART7 receive buffer register(high 8bit)
;
abt_u7rb		.btequ		11,u7rb		; Arbitration lost detect flag
oer_u7rb		.btequ		12,u7rb		; Overrun error flag
fer_u7rb		.btequ		13,u7rb		; Framing error flag
per_u7rb		.btequ		14,u7rb		; Parity error flag
sum_u7rb		.btequ		15,u7rb		; Error sum flag
;
;*-----------------------------------------------------------------------------*
;*  Timer B3,4,5 Count Start Flag                                              *
;*-----------------------------------------------------------------------------*
tbsr		.equ	0300h
;
tb3s			.btequ		5,tbsr		; Timer B3 count start flag
tb4s			.btequ		6,tbsr		; Timer B4 count start flag
tb5s			.btequ		7,tbsr		; Timer B5 count start flag
;
;*-----------------------------------------------------------------------------*
;*  Timer A1-1 Register                                                        *
;*-----------------------------------------------------------------------------*
ta11		.equ	0302h
;
;*-----------------------------------------------------------------------------*
;*  Timer A2-1 Register                                                        *
;*-----------------------------------------------------------------------------*
ta21		.equ	0304h
;
;*-----------------------------------------------------------------------------*
;*  Timer A4-1 Register                                                        *
;*-----------------------------------------------------------------------------*
ta41		.equ	0306h
;
;*-----------------------------------------------------------------------------*
;*  Three-Phase PWM Control Register 0                                         *
;*-----------------------------------------------------------------------------*
invc0		.equ	0308h
;
inv00			.btequ		0,invc0		; Interrupt enable output polarity select bit
inv01			.btequ		1,invc0		; Interrupt enable output specification bit
inv02			.btequ		2,invc0		; Mode select bit
inv03			.btequ		3,invc0		; Output control bit
inv04			.btequ		4,invc0		; Positive-and negativephases concurrent active disable function bit
inv05			.btequ		5,invc0		; Positive-and negativephases concurrent active output detect flag
inv06			.btequ		6,invc0		; Modulation mode select bit
inv07			.btequ		7,invc0		; Software trigger select bit
;
;*-----------------------------------------------------------------------------*
;*  Three-Phase PWM Control Register 1                                         *
;*-----------------------------------------------------------------------------*
invc1		.equ	0309h
;
inv10			.btequ		0,invc1		; Timer A1, A2, and A4 start trigger select bit
inv11			.btequ		1,invc1		; Timer A1-1, A2-1 and A4-1 control bit
inv12			.btequ		2,invc1		; Dead time timer count source select bit
inv13			.btequ		3,invc1		; Carrier wave detect bit
inv14			.btequ		4,invc1		; Output polarity control bit
inv15			.btequ		5,invc1		; Dead time disable bit
inv16			.btequ		6,invc1		; Dead time timer trigger select bit
;
;*-----------------------------------------------------------------------------*
;*  Three-Phase Output Buffer Register 0                                       *
;*-----------------------------------------------------------------------------*
idb0		.equ	030Ah
;
du0				.btequ		0,idb0		; U-phase output buffer 0
dub0			.btequ		1,idb0		; U~-phase output buffer 0
dv0				.btequ		2,idb0		; V-phase output buffer 0
dvb0			.btequ		3,idb0		; V~-phase output buffer 0
dw0				.btequ		4,idb0		; W-phase output buffer 0
dwb0			.btequ		5,idb0		; W~-phase output buffer 0
;
;*-----------------------------------------------------------------------------*
;*  Three-Phase Output Buffer Register 1                                       *
;*-----------------------------------------------------------------------------*
idb1		.equ	030Bh
;
du1				.btequ		0,idb1		; U-phase output buffer 1
dub1			.btequ		1,idb1		; U~-phase output buffer 1
dv1				.btequ		2,idb1		; V-phase output buffer 1
dvb1			.btequ		3,idb1		; V~-phase output buffer 1
dw1				.btequ		4,idb1		; W-phase output buffer 1
dwb1			.btequ		5,idb1		; W~-phase output buffer 1
;
;*-----------------------------------------------------------------------------*
;*  Dead Time Timer                                                            *
;*-----------------------------------------------------------------------------*
dtt			.equ	030Ch
;
;*-----------------------------------------------------------------------------*
;*  Timer B2 Interrupt Generation Frequency Set Counter                        *
;*-----------------------------------------------------------------------------*
ictb2		.equ	030Dh
;
;*-----------------------------------------------------------------------------*
;*  Timer B3 Register                                                          *
;*-----------------------------------------------------------------------------*
tb3			.equ	0310h
;
;*-----------------------------------------------------------------------------*
;*  Timer B4 Register                                                          *
;*-----------------------------------------------------------------------------*
tb4			.equ	0312h
;
;*-----------------------------------------------------------------------------*
;*  Timer B5 Register                                                          *
;*-----------------------------------------------------------------------------*
tb5			.equ	0314h
;
;*-----------------------------------------------------------------------------*
;*  Timer B3 Mode Register                                                     *
;*-----------------------------------------------------------------------------*
tb3mr		.equ	031Bh
;
tmod0_tb3mr		.btequ		0,tb3mr		; Operation mode select bit
tmod1_tb3mr		.btequ		1,tb3mr		; Operation mode select bit
mr0_tb3mr		.btequ		2,tb3mr		; Function varies with each operation mode
mr1_tb3mr		.btequ		3,tb3mr		; Function varies with each operation mode
mr3_tb3mr		.btequ		5,tb3mr		; Function varies with each operation mode
tck0_tb3mr		.btequ		6,tb3mr		; Count source select bit(Function varies with each operation mode)
tck1_tb3mr		.btequ		7,tb3mr		; Count source select bit(Function varies with each operation mode)
;
;*-----------------------------------------------------------------------------*
;*  Timer B4 Mode Register                                                     *
;*-----------------------------------------------------------------------------*
tb4mr		.equ	031Ch
;
tmod0_tb4mr		.btequ		0,tb4mr		; Operation mode select bit
tmod1_tb4mr		.btequ		1,tb4mr		; Operation mode select bit
mr0_tb4mr		.btequ		2,tb4mr		; Function varies with each operation mode
mr1_tb4mr		.btequ		3,tb4mr		; Function varies with each operation mode
mr3_tb4mr		.btequ		5,tb4mr		; Function varies with each operation mode
tck0_tb4mr		.btequ		6,tb4mr		; Count source select bit(Function varies with each operation mode)
tck1_tb4mr		.btequ		7,tb4mr		; Count source select bit(Function varies with each operation mode)
;
;*-----------------------------------------------------------------------------*
;*  Timer B5 Mode Register                                                     *
;*-----------------------------------------------------------------------------*
tb5mr		.equ	031Dh
;
tmod0_tb5mr		.btequ		0,tb5mr		; Operation mode select bit
tmod1_tb5mr		.btequ		1,tb5mr		; Operation mode select bit
mr0_tb5mr		.btequ		2,tb5mr		; Function varies with each operation mode
mr1_tb5mr		.btequ		3,tb5mr		; Function varies with each operation mode
mr3_tb5mr		.btequ		5,tb5mr		; Function varies with each operation mode
tck0_tb5mr		.btequ		6,tb5mr		; Count source select bit(Function varies with each operation mode)
tck1_tb5mr		.btequ		7,tb5mr		; Count source select bit(Function varies with each operation mode)
;
;*-----------------------------------------------------------------------------*
;*  Count Start Flag                                                           *
;*-----------------------------------------------------------------------------*
tabsr		.equ	0320h
;
ta0s			.btequ		0,tabsr		; Timer A0 count start flag
ta1s			.btequ		1,tabsr		; Timer A1 count start flag
ta2s			.btequ		2,tabsr		; Timer A2 count start flag
ta3s			.btequ		3,tabsr		; Timer A3 count start flag
ta4s			.btequ		4,tabsr		; Timer A4 count start flag
tb0s			.btequ		5,tabsr		; Timer B0 count start flag
tb1s			.btequ		6,tabsr		; Timer B1 count start flag
tb2s			.btequ		7,tabsr		; Timer B2 count start flag
;
;*-----------------------------------------------------------------------------*
;*  One-Shot Start Flag                                                        *
;*-----------------------------------------------------------------------------*
onsf		.equ	0322h
;
ta0os			.btequ		0,onsf		; Timer A0 one-shot start flag
ta1os			.btequ		1,onsf		; Timer A1 one-shot start flag
ta2os			.btequ		2,onsf		; Timer A2 one-shot start flag
ta3os			.btequ		3,onsf		; Timer A3 one-shot start flag
ta4os			.btequ		4,onsf		; Timer A4 one-shot start flag
tazie			.btequ		5,onsf		; Z-phase input enable bit
ta0tgl			.btequ		6,onsf		; Timer A0 event/trigger select bit
ta0tgh			.btequ		7,onsf		; Timer A0 event/trigger select bit
;
;*-----------------------------------------------------------------------------*
;*  Trigger Select Register                                                    *
;*-----------------------------------------------------------------------------*
trgsr		.equ	0323h
;
ta1tgl			.btequ		0,trgsr		; Timer A1 event/trigger select bit
ta1tgh			.btequ		1,trgsr		; Timer A1 event/trigger select bit
ta2tgl			.btequ		2,trgsr		; Timer A2 event/trigger select bit
ta2tgh			.btequ		3,trgsr		; Timer A2 event/trigger select bit
ta3tgl			.btequ		4,trgsr		; Timer A3 event/trigger select bit
ta3tgh			.btequ		5,trgsr		; Timer A3 event/trigger select bit
ta4tgl			.btequ		6,trgsr		; Timer A4 event/trigger select bit
ta4tgh			.btequ		7,trgsr		; Timer A4 event/trigger select bit
;
;*-----------------------------------------------------------------------------*
;*  Up/Down Flag                                                               *
;*-----------------------------------------------------------------------------*
udf			.equ	0324h
;
ta0ud			.btequ		0,udf		; Timer A0 up/down flag
ta1ud			.btequ		1,udf		; Timer A1 up/down flag
ta2ud			.btequ		2,udf		; Timer A2 up/down flag
ta3ud			.btequ		3,udf		; Timer A3 up/down flag
ta4ud			.btequ		4,udf		; Timer A4 up/down flag
ta2p			.btequ		5,udf		; Timer A2 two-phase pulse signal processing select bit
ta3p			.btequ		6,udf		; Timer A3 two-phase pulse signal processing select bit
ta4p			.btequ		7,udf		; Timer A4 two-phase pulse signal processing select bit
;
;*-----------------------------------------------------------------------------*
;*  Timer A0 Register                                                          *
;*-----------------------------------------------------------------------------*
ta0			.equ	0326h
;
;*-----------------------------------------------------------------------------*
;*  Timer A1 Register                                                          *
;*-----------------------------------------------------------------------------*
ta1			.equ	0328h
;
;*-----------------------------------------------------------------------------*
;*  Timer A2 Register                                                          *
;*-----------------------------------------------------------------------------*
ta2			.equ	032Ah
;
;*-----------------------------------------------------------------------------*
;*  Timer A3 Register                                                          *
;*-----------------------------------------------------------------------------*
ta3			.equ	032Ch
;
;*-----------------------------------------------------------------------------*
;*  Timer A4 Register                                                          *
;*-----------------------------------------------------------------------------*
ta4			.equ	032Eh
;
;*-----------------------------------------------------------------------------*
;*  Timer B0 Register                                                          *
;*-----------------------------------------------------------------------------*
tb0			.equ	0330h
;
;*-----------------------------------------------------------------------------*
;*  Timer B1 Register                                                          *
;*-----------------------------------------------------------------------------*
tb1			.equ	0332h
;
;*-----------------------------------------------------------------------------*
;*  Timer B2 Register                                                          *
;*-----------------------------------------------------------------------------*
tb2			.equ	0334h
;
;*-----------------------------------------------------------------------------*
;*  Timer A0 Mode Register                                                     *
;*-----------------------------------------------------------------------------*
ta0mr		.equ	0336h
;
tmod0_ta0mr		.btequ		0,ta0mr		; Operation mode select bit
tmod1_ta0mr		.btequ		1,ta0mr		; Operation mode select bit
mr0_ta0mr		.btequ		2,ta0mr		; Function varies with each operation mode
mr1_ta0mr		.btequ		3,ta0mr		; Function varies with each operation mode
mr2_ta0mr		.btequ		4,ta0mr		; Function varies with each operation mode
mr3_ta0mr		.btequ		5,ta0mr		; Function varies with each operation mode
tck0_ta0mr		.btequ		6,ta0mr		; Count source select bit(Function varies with each operation mode)
tck1_ta0mr		.btequ		7,ta0mr		; Count source select bit(Function varies with each operation mode)
;
;*-----------------------------------------------------------------------------*
;*  Timer A1 Mode Register                                                     *
;*-----------------------------------------------------------------------------*
ta1mr		.equ	0337h
;
tmod0_ta1mr		.btequ		0,ta1mr		; Operation mode select bit
tmod1_ta1mr		.btequ		1,ta1mr		; Operation mode select bit
mr0_ta1mr		.btequ		2,ta1mr		; Function varies with each operation mode
mr1_ta1mr		.btequ		3,ta1mr		; Function varies with each operation mode
mr2_ta1mr		.btequ		4,ta1mr		; Function varies with each operation mode
mr3_ta1mr		.btequ		5,ta1mr		; Function varies with each operation mode
tck0_ta1mr		.btequ		6,ta1mr		; Count source select bit(Function varies with each operation mode)
tck1_ta1mr		.btequ		7,ta1mr		; Count source select bit(Function varies with each operation mode)
;
;*-----------------------------------------------------------------------------*
;*  Timer A2 Mode Register                                                     *
;*-----------------------------------------------------------------------------*
ta2mr		.equ	0338h
;
tmod0_ta2mr		.btequ		0,ta2mr		; Operation mode select bit
tmod1_ta2mr		.btequ		1,ta2mr		; Operation mode select bit
mr0_ta2mr		.btequ		2,ta2mr		; Function varies with each operation mode
mr1_ta2mr		.btequ		3,ta2mr		; Function varies with each operation mode
mr2_ta2mr		.btequ		4,ta2mr		; Function varies with each operation mode
mr3_ta2mr		.btequ		5,ta2mr		; Function varies with each operation mode
tck0_ta2mr		.btequ		6,ta2mr		; Count source select bit(Function varies with each operation mode)
tck1_ta2mr		.btequ		7,ta2mr		; Count source select bit(Function varies with each operation mode)
;
;*-----------------------------------------------------------------------------*
;*  Timer A3 Mode Register                                                     *
;*-----------------------------------------------------------------------------*
ta3mr		.equ	0339h
;
tmod0_ta3mr		.btequ		0,ta3mr		; Operation mode select bit
tmod1_ta3mr		.btequ		1,ta3mr		; Operation mode select bit
mr0_ta3mr		.btequ		2,ta3mr		; Function varies with each operation mode
mr1_ta3mr		.btequ		3,ta3mr		; Function varies with each operation mode
mr2_ta3mr		.btequ		4,ta3mr		; Function varies with each operation mode
mr3_ta3mr		.btequ		5,ta3mr		; Function varies with each operation mode
tck0_ta3mr		.btequ		6,ta3mr		; Count source select bit(Function varies with each operation mode)
tck1_ta3mr		.btequ		7,ta3mr		; Count source select bit(Function varies with each operation mode)
;
;*-----------------------------------------------------------------------------*
;*  Timer A4 Mode Register                                                     *
;*-----------------------------------------------------------------------------*
ta4mr		.equ	033Ah
;
tmod0_ta4mr		.btequ		0,ta4mr		; Operation mode select bit
tmod1_ta4mr		.btequ		1,ta4mr		; Operation mode select bit
mr0_ta4mr		.btequ		2,ta4mr		; Function varies with each operation mode
mr1_ta4mr		.btequ		3,ta4mr		; Function varies with each operation mode
mr2_ta4mr		.btequ		4,ta4mr		; Function varies with each operation mode
mr3_ta4mr		.btequ		5,ta4mr		; Function varies with each operation mode
tck0_ta4mr		.btequ		6,ta4mr		; Count source select bit(Function varies with each operation mode)
tck1_ta4mr		.btequ		7,ta4mr		; Count source select bit(Function varies with each operation mode)
;
;*-----------------------------------------------------------------------------*
;*  Timer B0 Mode Register                                                     *
;*-----------------------------------------------------------------------------*
tb0mr		.equ	033Bh
;
tmod0_tb0mr		.btequ		0,tb0mr		; Operation mode select bit
tmod1_tb0mr		.btequ		1,tb0mr		; Operation mode select bit
mr0_tb0mr		.btequ		2,tb0mr		; Function varies with each operation mode
mr1_tb0mr		.btequ		3,tb0mr		; Function varies with each operation mode
mr3_tb0mr		.btequ		5,tb0mr		; Function varies with each operation mode
tck0_tb0mr		.btequ		6,tb0mr		; Count source select bit(Function varies with each operation mode)
tck1_tb0mr		.btequ		7,tb0mr		; Count source select bit(Function varies with each operation mode)
;
;*-----------------------------------------------------------------------------*
;*  Timer B1 Mode Register                                                     *
;*-----------------------------------------------------------------------------*
tb1mr		.equ	033Ch
;
tmod0_tb1mr		.btequ		0,tb1mr		; Operation mode select bit
tmod1_tb1mr		.btequ		1,tb1mr		; Operation mode select bit
mr0_tb1mr		.btequ		2,tb1mr		; Function varies with each operation mode
mr1_tb1mr		.btequ		3,tb1mr		; Function varies with each operation mode
mr3_tb1mr		.btequ		5,tb1mr		; Function varies with each operation mode
tck0_tb1mr		.btequ		6,tb1mr		; Count source select bit(Function varies with each operation mode)
tck1_tb1mr		.btequ		7,tb1mr		; Count source select bit(Function varies with each operation mode)
;
;*-----------------------------------------------------------------------------*
;*  Timer B2 Mode Register                                                     *
;*-----------------------------------------------------------------------------*
tb2mr		.equ	033Dh
;
tmod0_tb2mr		.btequ		0,tb2mr		; Operation mode select bit
tmod1_tb2mr		.btequ		1,tb2mr		; Operation mode select bit
mr0_tb2mr		.btequ		2,tb2mr		; Function varies with each operation mode
mr1_tb2mr		.btequ		3,tb2mr		; Function varies with each operation mode
mr3_tb2mr		.btequ		5,tb2mr		; Function varies with each operation mode
tck0_tb2mr		.btequ		6,tb2mr		; Count source select bit(Function varies with each operation mode)
tck1_tb2mr		.btequ		7,tb2mr		; Count source select bit(Function varies with each operation mode)
;
;*-----------------------------------------------------------------------------*
;*  Timer B2 Special Mode Register                                             *
;*-----------------------------------------------------------------------------*
tb2sc		.equ	033Eh
;
pwcon			.btequ		0,tb2sc		; Timer B2 reload timing switch bit
ivpcr1			.btequ		1,tb2sc		; Three-phase output port SD~ control bit 1
;
;*-----------------------------------------------------------------------------*
;*  Pull-Up Control Register 0                                                 *
;*-----------------------------------------------------------------------------*
pur0		.equ	0360h
;
pu00			.btequ		0,pur0		; P0_0 to P0_3 pull-up
pu01			.btequ		1,pur0		; P0_4 to P0_7 pull-up
pu02			.btequ		2,pur0		; P1_0 to P1_3 pull-up
pu03			.btequ		3,pur0		; P1_4 to P1_7 pull-up
pu04			.btequ		4,pur0		; P2_0 to P2_3 pull-up
pu05			.btequ		5,pur0		; P2_4 to P2_7 pull-up
pu06			.btequ		6,pur0		; P3_0 to P3_3 pull-up
pu07			.btequ		7,pur0		; P3_4 to P3_7 pull-up
;
;*-----------------------------------------------------------------------------*
;*  Pull-Up Control Register 1                                                 *
;*-----------------------------------------------------------------------------*
pur1		.equ	0361h
;
pu10			.btequ		0,pur1		; P4_0 to P4_3 pull-up
pu11			.btequ		1,pur1		; P4_4 to P4_7 pull-up
pu12			.btequ		2,pur1		; P5_0 to P5_3 pull-up
pu13			.btequ		3,pur1		; P5_4 to P5_7 pull-up
pu14			.btequ		4,pur1		; P6_0 to P6_3 pull-up
pu15			.btequ		5,pur1		; P6_4 to P6_7 pull-up
pu16			.btequ		6,pur1		; P7_2 to P7_3 pull-up
pu17			.btequ		7,pur1		; P7_4 to P7_7 pull-up
;
;*-----------------------------------------------------------------------------*
;*  Pull-Up Control Register 2                                                 *
;*-----------------------------------------------------------------------------*
pur2		.equ	0362h
;
pu20			.btequ		0,pur2		; P8_0 to P8_3 pull-up
pu21			.btequ		1,pur2		; P8_4 to P8_7 pull-up
pu22			.btequ		2,pur2		; P9_0 to P9_3 pull-up
pu23			.btequ		3,pur2		; P9_4 to P9_7 pull-up
pu24			.btequ		4,pur2		; P10_0 to P10_3 pull-up
pu25			.btequ		5,pur2		; P10_4 to P10_7 pull-up
;
;*-----------------------------------------------------------------------------*
;*  Port Control Register                                                      *
;*-----------------------------------------------------------------------------*
pcr			.equ	0366h
;
pcr0			.btequ		0,pcr		; Port P1 control bit
pcr5			.btequ		5,pcr		; INT6~ input enable bit
pcr6			.btequ		6,pcr		; INT7~ input enable bit
pcr7			.btequ		7,pcr		; Key input enable bit
;
;*-----------------------------------------------------------------------------*
;*  Count Source Protection Mode Register                                      *
;*-----------------------------------------------------------------------------*
cspr		.equ	037Ch
;
cspro			.btequ		7,cspr		; Count source protection mode select bit
;
;*-----------------------------------------------------------------------------*
;*  Watchdog Timer Reset Register                                              *
;*-----------------------------------------------------------------------------*
wdtr		.equ	037Dh
;
;*-----------------------------------------------------------------------------*
;*  Watchdog Timer Start Register                                              *
;*-----------------------------------------------------------------------------*
wdts		.equ	037Eh
;
;*-----------------------------------------------------------------------------*
;*  Watchdog Timer Control Register                                            *
;*-----------------------------------------------------------------------------*
wdc			.equ	037Fh
;
wdc7			.btequ		7,wdc		; Prescaler select bit
;
;*-----------------------------------------------------------------------------*
;*  DMA2 Source Select Register                                                *
;*-----------------------------------------------------------------------------*
dm2sl		.equ	0390h
;
dsel0_dm2sl		.btequ		0,dm2sl		; DMA request source select bit
dsel1_dm2sl		.btequ		1,dm2sl		; DMA request source select bit
dsel2_dm2sl		.btequ		2,dm2sl		; DMA request source select bit
dsel3_dm2sl		.btequ		3,dm2sl		; DMA request source select bit
dsel4_dm2sl		.btequ		4,dm2sl		; DMA request source select bit
dms_dm2sl		.btequ		6,dm2sl		; DMA request source expansion select bit
dsr_dm2sl		.btequ		7,dm2sl		; Software DMA request bit
;
;*-----------------------------------------------------------------------------*
;*  DMA3 Source Select Register                                                *
;*-----------------------------------------------------------------------------*
dm3sl		.equ	0392h
;
dsel0_dm3sl		.btequ		0,dm3sl		; DMA request source select bit
dsel1_dm3sl		.btequ		1,dm3sl		; DMA request source select bit
dsel2_dm3sl		.btequ		2,dm3sl		; DMA request source select bit
dsel3_dm3sl		.btequ		3,dm3sl		; DMA request source select bit
dsel4_dm3sl		.btequ		4,dm3sl		; DMA request source select bit
dms_dm3sl		.btequ		6,dm3sl		; DMA request source expansion select bit
dsr_dm3sl		.btequ		7,dm3sl		; Software DMA request bit
;
;*-----------------------------------------------------------------------------*
;*  DMA0 Source Select Register                                                *
;*-----------------------------------------------------------------------------*
dm0sl		.equ	0398h
;
dsel0_dm0sl		.btequ		0,dm0sl		; DMA request source select bit
dsel1_dm0sl		.btequ		1,dm0sl		; DMA request source select bit
dsel2_dm0sl		.btequ		2,dm0sl		; DMA request source select bit
dsel3_dm0sl		.btequ		3,dm0sl		; DMA request source select bit
dsel4_dm0sl		.btequ		4,dm0sl		; DMA request source select bit
dms_dm0sl		.btequ		6,dm0sl		; DMA request source expansion select bit
dsr_dm0sl		.btequ		7,dm0sl		; Software DMA request bit
;
;*-----------------------------------------------------------------------------*
;*  DMA1 Source Select Register                                                *
;*-----------------------------------------------------------------------------*
dm1sl		.equ	039Ah
;
dsel0_dm1sl		.btequ		0,dm1sl		; DMA request source select bit
dsel1_dm1sl		.btequ		1,dm1sl		; DMA request source select bit
dsel2_dm1sl		.btequ		2,dm1sl		; DMA request source select bit
dsel3_dm1sl		.btequ		3,dm1sl		; DMA request source select bit
dsel4_dm1sl		.btequ		4,dm1sl		; DMA request source select bit
dms_dm1sl		.btequ		6,dm1sl		; DMA request source expansion select bit
dsr_dm1sl		.btequ		7,dm1sl		; Software DMA request bit
;
;*-----------------------------------------------------------------------------*
;*  CRC Data Register                                                          *
;*-----------------------------------------------------------------------------*
crcd		.equ	03BCh
;
crcdl		.equ	crcd				; CRC Data Register(low 8bit)
crcdh		.equ	crcd+1				; CRC Data Register(high 8bit)
;
;*-----------------------------------------------------------------------------*
;*  CRC Input Register                                                         *
;*-----------------------------------------------------------------------------*
crcin		.equ	03BEh
;
;*-----------------------------------------------------------------------------*
;*  A/D Register 0                                                             *
;*-----------------------------------------------------------------------------*
ad0			.equ	03C0h
;
ad0l		.equ	ad0					; A/D Register 0(low 8bit)
ad0h		.equ	ad0+1				; A/D Register 0(high 8bit)
;
;*-----------------------------------------------------------------------------*
;*  A/D Register 1                                                             *
;*-----------------------------------------------------------------------------*
ad1			.equ	03C2h
;
ad1l		.equ	ad1					; A/D Register 1(low 8bit)
ad1h		.equ	ad1+1				; A/D Register 1(high 8bit)
;
;*-----------------------------------------------------------------------------*
;*  A/D Register 2                                                             *
;*-----------------------------------------------------------------------------*
ad2			.equ	03C4h
;
ad2l		.equ	ad2					; A/D Register 2(low 8bit)
ad2h		.equ	ad2+1				; A/D Register 2(high 8bit)
;
;*-----------------------------------------------------------------------------*
;*  A/D Register 3                                                             *
;*-----------------------------------------------------------------------------*
ad3			.equ	03C6h
;
ad3l		.equ	ad3					; A/D Register 3(low 8bit)
ad3h		.equ	ad3+1				; A/D Register 3(high 8bit)
;
;*-----------------------------------------------------------------------------*
;*  A/D Register 4                                                             *
;*-----------------------------------------------------------------------------*
ad4			.equ	03C8h
;
ad4l		.equ	ad4					; A/D Register 4(low 8bit)
ad4h		.equ	ad4+1				; A/D Register 4(high 8bit)
;
;*-----------------------------------------------------------------------------*
;*  A/D Register 5                                                             *
;*-----------------------------------------------------------------------------*
ad5			.equ	03CAh
;
ad5l		.equ	ad5					; A/D Register 5(low 8bit)
ad5h		.equ	ad5+1				; A/D Register 5(high 8bit)
;
;*-----------------------------------------------------------------------------*
;*  A/D Register 6                                                             *
;*-----------------------------------------------------------------------------*
ad6			.equ	03CCh
;
ad6l		.equ	ad6					; A/D Register 6(low 8bit)
ad6h		.equ	ad6+1				; A/D Register 6(high 8bit)
;
;*-----------------------------------------------------------------------------*
;*  A/D Register 7                                                             *
;*-----------------------------------------------------------------------------*
ad7			.equ	03CEh
;
ad7l		.equ	ad7					; A/D Register 7(low 8bit)
ad7h		.equ	ad7+1				; A/D Register 7(high 8bit)
;
;*-----------------------------------------------------------------------------*
;*  A/D Control Register 2                                                     *
;*-----------------------------------------------------------------------------*
adcon2		.equ	03D4h
;
adgsel0			.btequ		1,adcon2	; A/D input group select bit
adgsel1			.btequ		2,adcon2	; A/D input group select bit
cks2			.btequ		4,adcon2	; Frequency select bit 2
;
;*-----------------------------------------------------------------------------*
;*  A/D Control Register 0                                                     *
;*-----------------------------------------------------------------------------*
adcon0		.equ	03D6h
;
ch0				.btequ		0,adcon0	; Analog input pin select bit
ch1				.btequ		1,adcon0	; Analog input pin select bit
ch2				.btequ		2,adcon0	; Analog input pin select bit
md0				.btequ		3,adcon0	; A/D operation mode select bit 0
md1				.btequ		4,adcon0	; A/D operation mode select bit 0
trg				.btequ		5,adcon0	; Trigger select bit
adst			.btequ		6,adcon0	; A/D conversion start flag
cks0			.btequ		7,adcon0	; Frequency select bit 0
;
;*-----------------------------------------------------------------------------*
;*  A/D Control Register 1                                                     *
;*-----------------------------------------------------------------------------*
adcon1		.equ	03D7h
;
scan0			.btequ		0,adcon1	; A/D sweep pin select
scan1			.btequ		1,adcon1	; A/D sweep pin select
md2				.btequ		2,adcon1	; A/D operation mode select bit 1
cks1			.btequ		4,adcon1	; Frequency select bit 1
adstby			.btequ		5,adcon1	; A/D standby bit
adex0			.btequ		6,adcon1	; Extended pin select bit
adex1			.btequ		7,adcon1	; Extended pin select bit
;
;*-----------------------------------------------------------------------------*
;*  D/A0 Register                                                              *
;*-----------------------------------------------------------------------------*
da0			.equ	03D8h
;
;*-----------------------------------------------------------------------------*
;*  D/A1 Register                                                              *
;*-----------------------------------------------------------------------------*
da1			.equ	03DAh
;
;*-----------------------------------------------------------------------------*
;*  D/A Control Register                                                       *
;*-----------------------------------------------------------------------------*
dacon		.equ	03DCh
;
da0e			.btequ		0,dacon		; D/A 0 output enable bit
da1e			.btequ		1,dacon		; D/A 1 output enable bit
;
;*-----------------------------------------------------------------------------*
;*  Port P0 Register                                                           *
;*-----------------------------------------------------------------------------*
p0			.equ	03E0h
;
p0_0			.btequ		0,p0		; Port P0_0 bit
p0_1			.btequ		1,p0		; Port P0_1 bit
p0_2			.btequ		2,p0		; Port P0_2 bit
p0_3			.btequ		3,p0		; Port P0_3 bit
p0_4			.btequ		4,p0		; Port P0_4 bit
p0_5			.btequ		5,p0		; Port P0_5 bit
p0_6			.btequ		6,p0		; Port P0_6 bit
p0_7			.btequ		7,p0		; Port P0_7 bit
;
;*-----------------------------------------------------------------------------*
;*  Port P1 Register                                                           *
;*-----------------------------------------------------------------------------*
p1			.equ	03E1h
;
p1_0			.btequ		0,p1		; Port P1_0 bit
p1_1			.btequ		1,p1		; Port P1_1 bit
p1_2			.btequ		2,p1		; Port P1_2 bit
p1_3			.btequ		3,p1		; Port P1_3 bit
p1_4			.btequ		4,p1		; Port P1_4 bit
p1_5			.btequ		5,p1		; Port P1_5 bit
p1_6			.btequ		6,p1		; Port P1_6 bit
p1_7			.btequ		7,p1		; Port P1_7 bit
;
;*-----------------------------------------------------------------------------*
;*  Port P0 Direction Register                                                 *
;*-----------------------------------------------------------------------------*
pd0			.equ	03E2h
;
pd0_0			.btequ		0,pd0		; Port P0_0 direction bit
pd0_1			.btequ		1,pd0		; Port P0_1 direction bit
pd0_2			.btequ		2,pd0		; Port P0_2 direction bit
pd0_3			.btequ		3,pd0		; Port P0_3 direction bit
pd0_4			.btequ		4,pd0		; Port P0_4 direction bit
pd0_5			.btequ		5,pd0		; Port P0_5 direction bit
pd0_6			.btequ		6,pd0		; Port P0_6 direction bit
pd0_7			.btequ		7,pd0		; Port P0_7 direction bit
;
;*-----------------------------------------------------------------------------*
;*  Port P1 Direction Register                                                 *
;*-----------------------------------------------------------------------------*
pd1			.equ	03E3h
;
pd1_0			.btequ		0,pd1		; Port P1_0 direction bit
pd1_1			.btequ		1,pd1		; Port P1_1 direction bit
pd1_2			.btequ		2,pd1		; Port P1_2 direction bit
pd1_3			.btequ		3,pd1		; Port P1_3 direction bit
pd1_4			.btequ		4,pd1		; Port P1_4 direction bit
pd1_5			.btequ		5,pd1		; Port P1_5 direction bit
pd1_6			.btequ		6,pd1		; Port P1_6 direction bit
pd1_7			.btequ		7,pd1		; Port P1_7 direction bit
;
;*-----------------------------------------------------------------------------*
;*  Port P2 Register                                                           *
;*-----------------------------------------------------------------------------*
p2			.equ	03E4h
;
p2_0			.btequ		0,p2		; Port P2_0 bit
p2_1			.btequ		1,p2		; Port P2_1 bit
p2_2			.btequ		2,p2		; Port P2_2 bit
p2_3			.btequ		3,p2		; Port P2_3 bit
p2_4			.btequ		4,p2		; Port P2_4 bit
p2_5			.btequ		5,p2		; Port P2_5 bit
p2_6			.btequ		6,p2		; Port P2_6 bit
p2_7			.btequ		7,p2		; Port P2_7 bit
;
;*-----------------------------------------------------------------------------*
;*  Port P3 Register                                                           *
;*-----------------------------------------------------------------------------*
p3			.equ	03E5h
;
p3_0			.btequ		0,p3		; Port P3_0 bit
p3_1			.btequ		1,p3		; Port P3_1 bit
p3_2			.btequ		2,p3		; Port P3_2 bit
p3_3			.btequ		3,p3		; Port P3_3 bit
p3_4			.btequ		4,p3		; Port P3_4 bit
p3_5			.btequ		5,p3		; Port P3_5 bit
p3_6			.btequ		6,p3		; Port P3_6 bit
p3_7			.btequ		7,p3		; Port P3_7 bit
;
;*-----------------------------------------------------------------------------*
;*  Port P2 Direction Register                                                 *
;*-----------------------------------------------------------------------------*
pd2			.equ	03E6h
;
pd2_0			.btequ		0,pd2		; Port P2_0 direction bit
pd2_1			.btequ		1,pd2		; Port P2_1 direction bit
pd2_2			.btequ		2,pd2		; Port P2_2 direction bit
pd2_3			.btequ		3,pd2		; Port P2_3 direction bit
pd2_4			.btequ		4,pd2		; Port P2_4 direction bit
pd2_5			.btequ		5,pd2		; Port P2_5 direction bit
pd2_6			.btequ		6,pd2		; Port P2_6 direction bit
pd2_7			.btequ		7,pd2		; Port P2_7 direction bit
;
;*-----------------------------------------------------------------------------*
;*  Port P3 Direction Register                                                 *
;*-----------------------------------------------------------------------------*
pd3			.equ	03E7h
;
pd3_0			.btequ		0,pd3		; Port P3_0 direction bit
pd3_1			.btequ		1,pd3		; Port P3_1 direction bit
pd3_2			.btequ		2,pd3		; Port P3_2 direction bit
pd3_3			.btequ		3,pd3		; Port P3_3 direction bit
pd3_4			.btequ		4,pd3		; Port P3_4 direction bit
pd3_5			.btequ		5,pd3		; Port P3_5 direction bit
pd3_6			.btequ		6,pd3		; Port P3_6 direction bit
pd3_7			.btequ		7,pd3		; Port P3_7 direction bit
;
;*-----------------------------------------------------------------------------*
;*  Port P4 Register                                                           *
;*-----------------------------------------------------------------------------*
p4			.equ	03E8h
;
p4_0			.btequ		0,p4		; Port P4_0 bit
p4_1			.btequ		1,p4		; Port P4_1 bit
p4_2			.btequ		2,p4		; Port P4_2 bit
p4_3			.btequ		3,p4		; Port P4_3 bit
p4_4			.btequ		4,p4		; Port P4_4 bit
p4_5			.btequ		5,p4		; Port P4_5 bit
p4_6			.btequ		6,p4		; Port P4_6 bit
p4_7			.btequ		7,p4		; Port P4_7 bit
;
;*-----------------------------------------------------------------------------*
;*  Port P5 Register                                                           *
;*-----------------------------------------------------------------------------*
p5			.equ	03E9h
;
p5_0			.btequ		0,p5		; Port P5_0 bit
p5_1			.btequ		1,p5		; Port P5_1 bit
p5_2			.btequ		2,p5		; Port P5_2 bit
p5_3			.btequ		3,p5		; Port P5_3 bit
p5_4			.btequ		4,p5		; Port P5_4 bit
p5_5			.btequ		5,p5		; Port P5_5 bit
p5_6			.btequ		6,p5		; Port P5_6 bit
p5_7			.btequ		7,p5		; Port P5_7 bit
;
;*-----------------------------------------------------------------------------*
;*  Port P4 Direction Register                                                 *
;*-----------------------------------------------------------------------------*
pd4			.equ	03EAh
;
pd4_0			.btequ		0,pd4		; Port P4_0 direction bit
pd4_1			.btequ		1,pd4		; Port P4_1 direction bit
pd4_2			.btequ		2,pd4		; Port P4_2 direction bit
pd4_3			.btequ		3,pd4		; Port P4_3 direction bit
pd4_4			.btequ		4,pd4		; Port P4_4 direction bit
pd4_5			.btequ		5,pd4		; Port P4_5 direction bit
pd4_6			.btequ		6,pd4		; Port P4_6 direction bit
pd4_7			.btequ		7,pd4		; Port P4_7 direction bit
;
;*-----------------------------------------------------------------------------*
;*  Port P5 Direction Register                                                 *
;*-----------------------------------------------------------------------------*
pd5			.equ	03EBh
;
pd5_0			.btequ		0,pd5		; Port P5_0 direction bit
pd5_1			.btequ		1,pd5		; Port P5_1 direction bit
pd5_2			.btequ		2,pd5		; Port P5_2 direction bit
pd5_3			.btequ		3,pd5		; Port P5_3 direction bit
pd5_4			.btequ		4,pd5		; Port P5_4 direction bit
pd5_5			.btequ		5,pd5		; Port P5_5 direction bit
pd5_6			.btequ		6,pd5		; Port P5_6 direction bit
pd5_7			.btequ		7,pd5		; Port P5_7 direction bit
;
;*-----------------------------------------------------------------------------*
;*  Port P6 Register                                                           *
;*-----------------------------------------------------------------------------*
p6			.equ	03ECh
;
p6_0			.btequ		0,p6		; Port P6_0 bit
p6_1			.btequ		1,p6		; Port P6_1 bit
p6_2			.btequ		2,p6		; Port P6_2 bit
p6_3			.btequ		3,p6		; Port P6_3 bit
p6_4			.btequ		4,p6		; Port P6_4 bit
p6_5			.btequ		5,p6		; Port P6_5 bit
p6_6			.btequ		6,p6		; Port P6_6 bit
p6_7			.btequ		7,p6		; Port P6_7 bit
;
;*-----------------------------------------------------------------------------*
;*  Port P7 Register                                                           *
;*-----------------------------------------------------------------------------*
p7			.equ	03EDh
;
p7_0			.btequ		0,p7		; Port P7_0 bit
p7_1			.btequ		1,p7		; Port P7_1 bit
p7_2			.btequ		2,p7		; Port P7_2 bit
p7_3			.btequ		3,p7		; Port P7_3 bit
p7_4			.btequ		4,p7		; Port P7_4 bit
p7_5			.btequ		5,p7		; Port P7_5 bit
p7_6			.btequ		6,p7		; Port P7_6 bit
p7_7			.btequ		7,p7		; Port P7_7 bit
;
;*-----------------------------------------------------------------------------*
;*  Port P6 Direction Register                                                 *
;*-----------------------------------------------------------------------------*
pd6			.equ	03EEh
;
pd6_0			.btequ		0,pd6		; Port P6_0 direction bit
pd6_1			.btequ		1,pd6		; Port P6_1 direction bit
pd6_2			.btequ		2,pd6		; Port P6_2 direction bit
pd6_3			.btequ		3,pd6		; Port P6_3 direction bit
pd6_4			.btequ		4,pd6		; Port P6_4 direction bit
pd6_5			.btequ		5,pd6		; Port P6_5 direction bit
pd6_6			.btequ		6,pd6		; Port P6_6 direction bit
pd6_7			.btequ		7,pd6		; Port P6_7 direction bit
;
;*-----------------------------------------------------------------------------*
;*  Port P7 Direction Register                                                 *
;*-----------------------------------------------------------------------------*
pd7			.equ	03EFh
;
pd7_0			.btequ		0,pd7		; Port P7_0 direction bit
pd7_1			.btequ		1,pd7		; Port P7_1 direction bit
pd7_2			.btequ		2,pd7		; Port P7_2 direction bit
pd7_3			.btequ		3,pd7		; Port P7_3 direction bit
pd7_4			.btequ		4,pd7		; Port P7_4 direction bit
pd7_5			.btequ		5,pd7		; Port P7_5 direction bit
pd7_6			.btequ		6,pd7		; Port P7_6 direction bit
pd7_7			.btequ		7,pd7		; Port P7_7 direction bit
;
;*-----------------------------------------------------------------------------*
;*  Port P8 Register                                                           *
;*-----------------------------------------------------------------------------*
p8			.equ	03F0h
;
p8_0			.btequ		0,p8		; Port P8_0 bit
p8_1			.btequ		1,p8		; Port P8_1 bit
p8_2			.btequ		2,p8		; Port P8_2 bit
p8_3			.btequ		3,p8		; Port P8_3 bit
p8_4			.btequ		4,p8		; Port P8_4 bit
p8_5			.btequ		5,p8		; Port P8_5 bit
p8_6			.btequ		6,p8		; Port P8_6 bit
p8_7			.btequ		7,p8		; Port P8_7 bit
;
;*-----------------------------------------------------------------------------*
;*  Port P9 Register                                                           *
;*-----------------------------------------------------------------------------*
p9			.equ	03F1h
;
p9_0			.btequ		0,p9		; Port P9_0 bit
p9_1			.btequ		1,p9		; Port P9_1 bit
p9_2			.btequ		2,p9		; Port P9_2 bit
p9_3			.btequ		3,p9		; Port P9_3 bit
p9_4			.btequ		4,p9		; Port P9_4 bit
p9_5			.btequ		5,p9		; Port P9_5 bit
p9_6			.btequ		6,p9		; Port P9_6 bit
p9_7			.btequ		7,p9		; Port P9_7 bit
;
;*-----------------------------------------------------------------------------*
;*  Port P8 Direction Register                                                 *
;*-----------------------------------------------------------------------------*
pd8			.equ	03F2h
;
pd8_0			.btequ		0,pd8		; Port P8_0 direction bit
pd8_1			.btequ		1,pd8		; Port P8_1 direction bit
pd8_2			.btequ		2,pd8		; Port P8_2 direction bit
pd8_3			.btequ		3,pd8		; Port P8_3 direction bit
pd8_4			.btequ		4,pd8		; Port P8_4 direction bit
pd8_5			.btequ		5,pd8		; Port P8_5 direction bit
pd8_6			.btequ		6,pd8		; Port P8_6 direction bit
pd8_7			.btequ		7,pd8		; Port P8_7 direction bit
;
;*-----------------------------------------------------------------------------*
;*  Port P9 Direction Register                                                 *
;*-----------------------------------------------------------------------------*
pd9			.equ	03F3h
;
pd9_0			.btequ		0,pd9		; Port P9_0 direction bit
pd9_1			.btequ		1,pd9		; Port P9_1 direction bit
pd9_2			.btequ		2,pd9		; Port P9_2 direction bit
pd9_3			.btequ		3,pd9		; Port P9_3 direction bit
pd9_4			.btequ		4,pd9		; Port P9_4 direction bit
pd9_5			.btequ		5,pd9		; Port P9_5 direction bit
pd9_6			.btequ		6,pd9		; Port P9_6 direction bit
pd9_7			.btequ		7,pd9		; Port P9_7 direction bit
;
;*-----------------------------------------------------------------------------*
;*  Port P10 Register                                                          *
;*-----------------------------------------------------------------------------*
p10			.equ	03F4h
;
p10_0			.btequ		0,p10		; Port P10_0 bit
p10_1			.btequ		1,p10		; Port P10_1 bit
p10_2			.btequ		2,p10		; Port P10_2 bit
p10_3			.btequ		3,p10		; Port P10_3 bit
p10_4			.btequ		4,p10		; Port P10_4 bit
p10_5			.btequ		5,p10		; Port P10_5 bit
p10_6			.btequ		6,p10		; Port P10_6 bit
p10_7			.btequ		7,p10		; Port P10_7 bit
;
;*-----------------------------------------------------------------------------*
;*  Port P10 Direction Register                                                *
;*-----------------------------------------------------------------------------*
pd10		.equ	03F6h
;
pd10_0			.btequ		0,pd10		; Port P10_0 direction bit
pd10_1			.btequ		1,pd10		; Port P10_1 direction bit
pd10_2			.btequ		2,pd10		; Port P10_2 direction bit
pd10_3			.btequ		3,pd10		; Port P10_3 direction bit
pd10_4			.btequ		4,pd10		; Port P10_4 direction bit
pd10_5			.btequ		5,pd10		; Port P10_5 direction bit
pd10_6			.btequ		6,pd10		; Port P10_6 direction bit
pd10_7			.btequ		7,pd10		; Port P10_7 direction bit
;
;*** EOF ***********************************************************************
